From: Lu Baolu <baolu.lu@linux.intel.com> To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org> Cc: Ashok Raj <ashok.raj@intel.com>, Jacob Pan <jacob.jun.pan@linux.intel.com>, Guo Kaijie <Kaijie.Guo@intel.com>, Liu Yi L <yi.l.liu@intel.com>, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu <baolu.lu@linux.intel.com> Subject: [PATCH 2/5] iommu/vt-d: Fix unaligned addresses for intel_flush_svm_range_dev() Date: Thu, 31 Dec 2020 08:53:20 +0800 [thread overview] Message-ID: <20201231005323.2178523-2-baolu.lu@linux.intel.com> (raw) In-Reply-To: <20201231005323.2178523-1-baolu.lu@linux.intel.com> The VT-d hardware will ignore those Addr bits which have been masked by the AM field in the PASID-based-IOTLB invalidation descriptor. As the result, if the starting address in the descriptor is not aligned with the address mask, some IOTLB caches might not invalidate. Hence people will see below errors. [ 1093.704661] dmar_fault: 29 callbacks suppressed [ 1093.704664] DMAR: DRHD: handling fault status reg 3 [ 1093.712738] DMAR: [DMA Read] Request device [7a:02.0] PASID 2 fault addr 7f81c968d000 [fault reason 113] SM: Present bit in first-level paging entry is clear Fix this by using aligned address for PASID-based-IOTLB invalidation. Fixes: 1c4f88b7f1f92 ("iommu/vt-d: Shared virtual address in scalable mode") Reported-and-tested-by: Guo Kaijie <Kaijie.Guo@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> --- drivers/iommu/intel/svm.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 69566695d032..b16a4791acfb 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -118,8 +118,10 @@ void intel_svm_check(struct intel_iommu *iommu) iommu->flags |= VTD_FLAG_SVM_CAPABLE; } -static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev, - unsigned long address, unsigned long pages, int ih) +static void __flush_svm_range_dev(struct intel_svm *svm, + struct intel_svm_dev *sdev, + unsigned long address, + unsigned long pages, int ih) { struct qi_desc desc; @@ -170,6 +172,22 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d } } +static void intel_flush_svm_range_dev(struct intel_svm *svm, + struct intel_svm_dev *sdev, + unsigned long address, + unsigned long pages, int ih) +{ + unsigned long shift = ilog2(__roundup_pow_of_two(pages)); + unsigned long align = (1ULL << (VTD_PAGE_SHIFT + shift)); + unsigned long start = ALIGN_DOWN(address, align); + unsigned long end = ALIGN(address + (pages << VTD_PAGE_SHIFT), align); + + while (start < end) { + __flush_svm_range_dev(svm, sdev, start, align >> VTD_PAGE_SHIFT, ih); + start += align; + } +} + static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address, unsigned long pages, int ih) { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Lu Baolu <baolu.lu@linux.intel.com> To: Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org> Cc: Ashok Raj <ashok.raj@intel.com>, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Guo Kaijie <Kaijie.Guo@intel.com> Subject: [PATCH 2/5] iommu/vt-d: Fix unaligned addresses for intel_flush_svm_range_dev() Date: Thu, 31 Dec 2020 08:53:20 +0800 [thread overview] Message-ID: <20201231005323.2178523-2-baolu.lu@linux.intel.com> (raw) In-Reply-To: <20201231005323.2178523-1-baolu.lu@linux.intel.com> The VT-d hardware will ignore those Addr bits which have been masked by the AM field in the PASID-based-IOTLB invalidation descriptor. As the result, if the starting address in the descriptor is not aligned with the address mask, some IOTLB caches might not invalidate. Hence people will see below errors. [ 1093.704661] dmar_fault: 29 callbacks suppressed [ 1093.704664] DMAR: DRHD: handling fault status reg 3 [ 1093.712738] DMAR: [DMA Read] Request device [7a:02.0] PASID 2 fault addr 7f81c968d000 [fault reason 113] SM: Present bit in first-level paging entry is clear Fix this by using aligned address for PASID-based-IOTLB invalidation. Fixes: 1c4f88b7f1f92 ("iommu/vt-d: Shared virtual address in scalable mode") Reported-and-tested-by: Guo Kaijie <Kaijie.Guo@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> --- drivers/iommu/intel/svm.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 69566695d032..b16a4791acfb 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -118,8 +118,10 @@ void intel_svm_check(struct intel_iommu *iommu) iommu->flags |= VTD_FLAG_SVM_CAPABLE; } -static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev, - unsigned long address, unsigned long pages, int ih) +static void __flush_svm_range_dev(struct intel_svm *svm, + struct intel_svm_dev *sdev, + unsigned long address, + unsigned long pages, int ih) { struct qi_desc desc; @@ -170,6 +172,22 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d } } +static void intel_flush_svm_range_dev(struct intel_svm *svm, + struct intel_svm_dev *sdev, + unsigned long address, + unsigned long pages, int ih) +{ + unsigned long shift = ilog2(__roundup_pow_of_two(pages)); + unsigned long align = (1ULL << (VTD_PAGE_SHIFT + shift)); + unsigned long start = ALIGN_DOWN(address, align); + unsigned long end = ALIGN(address + (pages << VTD_PAGE_SHIFT), align); + + while (start < end) { + __flush_svm_range_dev(svm, sdev, start, align >> VTD_PAGE_SHIFT, ih); + start += align; + } +} + static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address, unsigned long pages, int ih) { -- 2.25.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2020-12-31 1:04 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-31 0:53 [PATCH 1/5] iommu/vt-d: Fix misuse of ALIGN in qi_flush_piotlb() Lu Baolu 2020-12-31 0:53 ` Lu Baolu 2020-12-31 0:53 ` Lu Baolu [this message] 2020-12-31 0:53 ` [PATCH 2/5] iommu/vt-d: Fix unaligned addresses for intel_flush_svm_range_dev() Lu Baolu 2021-01-05 19:03 ` Will Deacon 2021-01-05 19:03 ` Will Deacon 2021-01-06 1:09 ` Lu Baolu 2021-01-06 1:09 ` Lu Baolu 2021-01-07 23:52 ` Lu Baolu 2021-01-07 23:52 ` Lu Baolu 2021-01-08 14:09 ` Will Deacon 2021-01-08 14:09 ` Will Deacon 2021-01-08 14:30 ` Lu Baolu 2021-01-08 14:30 ` Lu Baolu 2020-12-31 0:53 ` [PATCH 3/5] iommu/vt-d: Remove unused dma map/unmap trace events Lu Baolu 2020-12-31 0:53 ` Lu Baolu 2021-01-05 19:04 ` Will Deacon 2021-01-05 19:04 ` Will Deacon 2021-01-06 1:14 ` Lu Baolu 2021-01-06 1:14 ` Lu Baolu 2021-01-07 14:40 ` Will Deacon 2021-01-07 14:40 ` Will Deacon 2021-01-08 0:00 ` Lu Baolu 2021-01-08 0:00 ` Lu Baolu 2020-12-31 0:53 ` [PATCH 4/5] Revert "iommu: Add quirk for Intel graphic devices in map_sg" Lu Baolu 2020-12-31 0:53 ` Lu Baolu 2020-12-31 0:53 ` [PATCH 5/5] iommu/vt-d: Fix lockdep splat in sva bind()/unbind() Lu Baolu 2020-12-31 0:53 ` Lu Baolu 2021-01-07 14:22 ` [PATCH 1/5] iommu/vt-d: Fix misuse of ALIGN in qi_flush_piotlb() Will Deacon 2021-01-07 14:22 ` Will Deacon
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