From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org
Cc: mturquette@baylibre.com, sboyd@kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH 0/5] clk: meson8b: video clock tree updates
Date: Mon, 4 Jan 2021 14:28:01 +0100 [thread overview]
Message-ID: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> (raw)
Hi Jerome,
this is a small set of updates for the video clocks. I have verified
these patches to be able to generate the video clocks for 1080P, 720P
and a few other video modes.
The main "mystery" is still how the rate doubling happens. However,
that doesn't affect these patches as with this rate doubling the
"hdmi_pll_lvds_out" (which is a parent of this tree) is doubled as
well. That's why I am sending these patches because even with this
unknown part about rate doubling they will still be valid once that
unknown part has been figured out.
Martin Blumenstingl (5):
clk: meson: meson8b: don't use MPLL1 as parent of vclk_in_sel
clk: meson: meson8b: define the rate range for the hdmi_pll_dco clock
clk: meson: meson8b: add the video clock divider tables
clk: meson: meson8b: add the HDMI PLL M/N parameters
clk: meson: meson8b: add the vid_pll_lvds_en gate clock
drivers/clk/meson/meson8b.c | 79 ++++++++++++++++++++++++++++++++++++-
drivers/clk/meson/meson8b.h | 3 +-
2 files changed, 79 insertions(+), 3 deletions(-)
--
2.30.0
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org
Cc: sboyd@kernel.org, mturquette@baylibre.com,
linux-kernel@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/5] clk: meson8b: video clock tree updates
Date: Mon, 4 Jan 2021 14:28:01 +0100 [thread overview]
Message-ID: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> (raw)
Hi Jerome,
this is a small set of updates for the video clocks. I have verified
these patches to be able to generate the video clocks for 1080P, 720P
and a few other video modes.
The main "mystery" is still how the rate doubling happens. However,
that doesn't affect these patches as with this rate doubling the
"hdmi_pll_lvds_out" (which is a parent of this tree) is doubled as
well. That's why I am sending these patches because even with this
unknown part about rate doubling they will still be valid once that
unknown part has been figured out.
Martin Blumenstingl (5):
clk: meson: meson8b: don't use MPLL1 as parent of vclk_in_sel
clk: meson: meson8b: define the rate range for the hdmi_pll_dco clock
clk: meson: meson8b: add the video clock divider tables
clk: meson: meson8b: add the HDMI PLL M/N parameters
clk: meson: meson8b: add the vid_pll_lvds_en gate clock
drivers/clk/meson/meson8b.c | 79 ++++++++++++++++++++++++++++++++++++-
drivers/clk/meson/meson8b.h | 3 +-
2 files changed, 79 insertions(+), 3 deletions(-)
--
2.30.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org
Cc: sboyd@kernel.org, mturquette@baylibre.com,
linux-kernel@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/5] clk: meson8b: video clock tree updates
Date: Mon, 4 Jan 2021 14:28:01 +0100 [thread overview]
Message-ID: <20210104132806.720558-1-martin.blumenstingl@googlemail.com> (raw)
Hi Jerome,
this is a small set of updates for the video clocks. I have verified
these patches to be able to generate the video clocks for 1080P, 720P
and a few other video modes.
The main "mystery" is still how the rate doubling happens. However,
that doesn't affect these patches as with this rate doubling the
"hdmi_pll_lvds_out" (which is a parent of this tree) is doubled as
well. That's why I am sending these patches because even with this
unknown part about rate doubling they will still be valid once that
unknown part has been figured out.
Martin Blumenstingl (5):
clk: meson: meson8b: don't use MPLL1 as parent of vclk_in_sel
clk: meson: meson8b: define the rate range for the hdmi_pll_dco clock
clk: meson: meson8b: add the video clock divider tables
clk: meson: meson8b: add the HDMI PLL M/N parameters
clk: meson: meson8b: add the vid_pll_lvds_en gate clock
drivers/clk/meson/meson8b.c | 79 ++++++++++++++++++++++++++++++++++++-
drivers/clk/meson/meson8b.h | 3 +-
2 files changed, 79 insertions(+), 3 deletions(-)
--
2.30.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
next reply other threads:[~2021-01-04 13:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-04 13:28 Martin Blumenstingl [this message]
2021-01-04 13:28 ` [PATCH 0/5] clk: meson8b: video clock tree updates Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
2021-01-04 13:28 ` [PATCH 1/5] clk: meson: meson8b: don't use MPLL1 as parent of vclk_in_sel Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
2021-01-04 13:28 ` [PATCH 2/5] clk: meson: meson8b: define the rate range for the hdmi_pll_dco clock Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
2021-01-04 13:28 ` [PATCH 3/5] clk: meson: meson8b: add the video clock divider tables Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
2021-01-04 13:28 ` [PATCH 4/5] clk: meson: meson8b: add the HDMI PLL M/N parameters Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
2021-01-04 13:28 ` [PATCH 5/5] clk: meson: meson8b: add the vid_pll_lvds_en gate clock Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
2021-01-04 13:28 ` Martin Blumenstingl
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