From: Sylvain Pelissier <sylvain.pelissier@gmail.com> Cc: Sylvain Pelissier <sylvain.pelissier@gmail.com>, "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, "open list:All patches CC here" <qemu-devel@nongnu.org>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: [PATCH v3] gdb: riscv: Add target description Date: Wed, 6 Jan 2021 11:32:54 +0100 [thread overview] Message-ID: <20210106103254.35615-1-sylvain.pelissier@gmail.com> (raw) Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> --- target/riscv/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 254cd83f8b..ed4971978b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static gchar *riscv_gdb_arch_name(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (riscv_cpu_is_32bit(env)) { + return g_strdup("riscv:rv32"); + } else { + return g_strdup("riscv:rv64"); + } +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; #endif + cc->gdb_arch_name = riscv_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_initialize = riscv_translate_init; cc->tlb_fill = riscv_cpu_tlb_fill; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Sylvain Pelissier <sylvain.pelissier@gmail.com> Cc: Sylvain Pelissier <sylvain.pelissier@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), qemu-devel@nongnu.org (open list:All patches CC here) Subject: [PATCH v3] gdb: riscv: Add target description Date: Wed, 6 Jan 2021 11:32:54 +0100 [thread overview] Message-ID: <20210106103254.35615-1-sylvain.pelissier@gmail.com> (raw) Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> --- target/riscv/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 254cd83f8b..ed4971978b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static gchar *riscv_gdb_arch_name(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (riscv_cpu_is_32bit(env)) { + return g_strdup("riscv:rv32"); + } else { + return g_strdup("riscv:rv64"); + } +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; #endif + cc->gdb_arch_name = riscv_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_initialize = riscv_translate_init; cc->tlb_fill = riscv_cpu_tlb_fill; -- 2.25.1
next reply other threads:[~2021-01-06 10:34 UTC|newest] Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-06 10:32 Sylvain Pelissier [this message] 2021-01-06 10:32 ` [PATCH v3] gdb: riscv: Add target description Sylvain Pelissier 2021-01-06 10:56 ` Bin Meng
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