From: Jernej Skrabec <jernej.skrabec@siol.net>
To: robh+dt@kernel.org, mripard@kernel.org, wens@csie.org
Cc: mchehab@kernel.org, linux-media@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, jernej.skrabec@siol.net,
linux-sunxi@googlegroups.com
Subject: [PATCH 2/2] ARM: dts: sun8i: r40: Add deinterlace node
Date: Wed, 6 Jan 2021 19:19:01 +0100 [thread overview]
Message-ID: <20210106181901.1324075-3-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20210106181901.1324075-1-jernej.skrabec@siol.net>
R40 contains deinterlace core compatible to that in H3. One peculiarity
is that RAM gate is shared with CSI1. User manual states it's separate
but that's not true. Shared gate was verified with BSP Linux code check
and with runtime tests (CPU crashed if CSI1 gate was not ungated).
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/boot/dts/sun8i-r40.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 7907569e7b5c..d5ad3b9efd12 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -190,6 +190,25 @@ mixer1_out_tcon_top: endpoint {
};
};
+ deinterlace: deinterlace@1400000 {
+ compatible = "allwinner,sun8i-r40-deinterlace",
+ "allwinner,sun8i-h3-deinterlace";
+ reg = <0x01400000 0x20000>;
+ clocks = <&ccu CLK_BUS_DEINTERLACE>,
+ <&ccu CLK_DEINTERLACE>,
+ /*
+ * NOTE: Contrary to what datasheet claims,
+ * DRAM deinterlace gate doesn't exist and
+ * it's shared with CSI1.
+ */
+ <&ccu CLK_DRAM_CSI1>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_DEINTERLACE>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&mbus 9>;
+ interconnect-names = "dma-mem";
+ };
+
syscon: system-control@1c00000 {
compatible = "allwinner,sun8i-r40-system-control",
"allwinner,sun4i-a10-system-control";
--
2.30.0
WARNING: multiple messages have this Message-ID (diff)
From: Jernej Skrabec <jernej.skrabec@siol.net>
To: robh+dt@kernel.org, mripard@kernel.org, wens@csie.org
Cc: devicetree@vger.kernel.org, jernej.skrabec@siol.net,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
mchehab@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-media@vger.kernel.org
Subject: [PATCH 2/2] ARM: dts: sun8i: r40: Add deinterlace node
Date: Wed, 6 Jan 2021 19:19:01 +0100 [thread overview]
Message-ID: <20210106181901.1324075-3-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20210106181901.1324075-1-jernej.skrabec@siol.net>
R40 contains deinterlace core compatible to that in H3. One peculiarity
is that RAM gate is shared with CSI1. User manual states it's separate
but that's not true. Shared gate was verified with BSP Linux code check
and with runtime tests (CPU crashed if CSI1 gate was not ungated).
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/boot/dts/sun8i-r40.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 7907569e7b5c..d5ad3b9efd12 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -190,6 +190,25 @@ mixer1_out_tcon_top: endpoint {
};
};
+ deinterlace: deinterlace@1400000 {
+ compatible = "allwinner,sun8i-r40-deinterlace",
+ "allwinner,sun8i-h3-deinterlace";
+ reg = <0x01400000 0x20000>;
+ clocks = <&ccu CLK_BUS_DEINTERLACE>,
+ <&ccu CLK_DEINTERLACE>,
+ /*
+ * NOTE: Contrary to what datasheet claims,
+ * DRAM deinterlace gate doesn't exist and
+ * it's shared with CSI1.
+ */
+ <&ccu CLK_DRAM_CSI1>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_DEINTERLACE>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&mbus 9>;
+ interconnect-names = "dma-mem";
+ };
+
syscon: system-control@1c00000 {
compatible = "allwinner,sun8i-r40-system-control",
"allwinner,sun4i-a10-system-control";
--
2.30.0
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next prev parent reply other threads:[~2021-01-06 18:13 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-06 18:18 [PATCH 0/2] ARM: dts: sun8i: r40: Add deinterlace node Jernej Skrabec
2021-01-06 18:18 ` Jernej Skrabec
2021-01-06 18:19 ` [PATCH 1/2] dt-bindings: media: Add Allwinner R40 deinterlace compatible Jernej Skrabec
2021-01-06 18:19 ` Jernej Skrabec
2021-01-06 18:19 ` Jernej Skrabec [this message]
2021-01-06 18:19 ` [PATCH 2/2] ARM: dts: sun8i: r40: Add deinterlace node Jernej Skrabec
2021-01-07 9:39 ` [PATCH 0/2] " Maxime Ripard
2021-01-07 9:39 ` Maxime Ripard
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