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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/23] target/arm: Fix MTE0_ACTIVE
Date: Fri,  8 Jan 2021 15:36:01 +0000	[thread overview]
Message-ID: <20210108153621.3868-4-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210108153621.3868-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

In 50244cc76abc we updated mte_check_fail to match the ARM
pseudocode, using the correct EL to select the TCF field.
But we failed to update MTE0_ACTIVE the same way, which led
to g_assert_not_reached().

Cc: qemu-stable@nongnu.org
Buglink: https://bugs.launchpad.net/bugs/1907137
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201221204426.88514-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2d0d4cd1e10..d077dd9ef51 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12928,7 +12928,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
         if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
             && tbid
             && !(env->pstate & PSTATE_TCO)
-            && (sctlr & SCTLR_TCF0)
+            && (sctlr & SCTLR_TCF)
             && allocation_tag_access_enabled(env, 0, sctlr)) {
             flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
         }
-- 
2.20.1



  parent reply	other threads:[~2021-01-08 15:40 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-08 15:35 [PULL 00/23] target-arm queue Peter Maydell
2021-01-08 15:35 ` [PULL 01/23] intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs Peter Maydell
2021-01-08 15:36 ` [PULL 02/23] hw/arm/virt: Remove virt machine state 'smp_cpus' Peter Maydell
2021-01-08 15:36 ` Peter Maydell [this message]
2021-01-08 15:36 ` [PULL 04/23] hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN Peter Maydell
2021-01-08 15:36 ` [PULL 05/23] target/arm: Correct store of FPSCR value via FPCXT_S Peter Maydell
2021-01-08 15:36 ` [PULL 06/23] target/arm: Implement FPCXT_NS fp system register Peter Maydell
2021-01-08 15:36 ` [PULL 07/23] target/arm: Implement Cortex-M55 model Peter Maydell
2021-01-08 15:36 ` [PULL 08/23] hw/arm/highbank: Drop dead KVM support code Peter Maydell
2021-01-08 15:36 ` [PULL 09/23] util/qemu-timer: Make timer_free() imply timer_del() Peter Maydell
2021-01-08 15:36 ` [PULL 10/23] scripts/coccinelle: New script to remove unnecessary timer_del() calls Peter Maydell
2021-01-08 15:36 ` [PULL 11/23] Remove superfluous " Peter Maydell
2021-01-08 15:36 ` [PULL 12/23] target/arm: Remove timer_del()/timer_deinit() before timer_free() Peter Maydell
2021-01-08 15:36 ` [PULL 13/23] digic-timer: Use ptimer_free() in the finalize function to avoid memleaks Peter Maydell
2021-01-08 15:36 ` [PULL 14/23] allwinner-a10-pit: " Peter Maydell
2021-01-08 15:36 ` [PULL 15/23] exynos4210_rtc: " Peter Maydell
2021-01-08 15:36 ` [PULL 16/23] exynos4210_pwm: " Peter Maydell
2021-01-08 15:36 ` [PULL 17/23] mss-timer: " Peter Maydell
2021-01-08 15:36 ` [PULL 18/23] musicpal: " Peter Maydell
2021-01-08 15:36 ` [PULL 19/23] exynos4210_mct: " Peter Maydell
2021-01-08 15:36 ` [PULL 20/23] hw/misc: imx6_ccm: Update PMU_MISC0 reset value Peter Maydell
2021-01-08 15:36 ` [PULL 21/23] hw/msic: imx6_ccm: Correct register value for silicon type Peter Maydell
2021-01-08 15:36 ` [PULL 22/23] hw/arm: sabrelite: Connect the Ethernet PHY at address 6 Peter Maydell
2021-01-08 15:36 ` [PULL 23/23] docs/system: arm: Add sabrelite board description Peter Maydell
2021-01-08 17:49 ` [PULL 00/23] target-arm queue Peter Maydell
2021-01-10 19:08   ` 罗勇刚(Yonggang Luo)

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