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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: coresight@lists.linaro.org, mathieu.poirier@linaro.org,
	anshuman.khandual@arm.com, mike.leach@linaro.org,
	leo.yan@linaro.org, linux-kernel@vger.kernel.org,
	jonathan.zhouwen@huawei.com, catalin.marinas@arm.com,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v7 10/28] coresight: etm4x: Add commentary on the registers
Date: Sun, 10 Jan 2021 22:48:32 +0000	[thread overview]
Message-ID: <20210110224850.1880240-11-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210110224850.1880240-1-suzuki.poulose@arm.com>

As we are about define a switch..case table for individual register
access by offset for implementing the system instruction support,
document the possible set of registers for each group to make
it easier to correlate.

Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes since v3
 - Fix commit description spelling mistake (Mathieu)
---
 drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++-------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index b6854f6fd666..3c2b49ffabc8 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -45,13 +45,13 @@
 #define TRCVDSACCTLR			0x0A4
 #define TRCVDARCCTLR			0x0A8
 /* Derived resources registers */
-#define TRCSEQEVRn(n)			(0x100 + (n * 4))
+#define TRCSEQEVRn(n)			(0x100 + (n * 4)) /* n = 0-2 */
 #define TRCSEQRSTEVR			0x118
 #define TRCSEQSTR			0x11C
 #define TRCEXTINSELR			0x120
-#define TRCCNTRLDVRn(n)			(0x140 + (n * 4))
-#define TRCCNTCTLRn(n)			(0x150 + (n * 4))
-#define TRCCNTVRn(n)			(0x160 + (n * 4))
+#define TRCCNTRLDVRn(n)			(0x140 + (n * 4)) /* n = 0-3 */
+#define TRCCNTCTLRn(n)			(0x150 + (n * 4)) /* n = 0-3 */
+#define TRCCNTVRn(n)			(0x160 + (n * 4)) /* n = 0-3 */
 /* ID registers */
 #define TRCIDR8				0x180
 #define TRCIDR9				0x184
@@ -60,7 +60,7 @@
 #define TRCIDR12			0x190
 #define TRCIDR13			0x194
 #define TRCIMSPEC0			0x1C0
-#define TRCIMSPECn(n)			(0x1C0 + (n * 4))
+#define TRCIMSPECn(n)			(0x1C0 + (n * 4)) /* n = 1-7 */
 #define TRCIDR0				0x1E0
 #define TRCIDR1				0x1E4
 #define TRCIDR2				0x1E8
@@ -69,9 +69,12 @@
 #define TRCIDR5				0x1F4
 #define TRCIDR6				0x1F8
 #define TRCIDR7				0x1FC
-/* Resource selection registers */
+/*
+ * Resource selection registers, n = 2-31.
+ * First pair (regs 0, 1) is always present and is reserved.
+ */
 #define TRCRSCTLRn(n)			(0x200 + (n * 4))
-/* Single-shot comparator registers */
+/* Single-shot comparator registers, n = 0-7 */
 #define TRCSSCCRn(n)			(0x280 + (n * 4))
 #define TRCSSCSRn(n)			(0x2A0 + (n * 4))
 #define TRCSSPCICRn(n)			(0x2C0 + (n * 4))
@@ -81,11 +84,13 @@
 #define TRCPDCR				0x310
 #define TRCPDSR				0x314
 /* Trace registers (0x318-0xEFC) */
-/* Comparator registers */
+/* Address Comparator registers n = 0-15 */
 #define TRCACVRn(n)			(0x400 + (n * 8))
 #define TRCACATRn(n)			(0x480 + (n * 8))
+/* Data Value Comparator Value registers, n = 0-7 */
 #define TRCDVCVRn(n)			(0x500 + (n * 16))
 #define TRCDVCMRn(n)			(0x580 + (n * 16))
+/* ContextID/Virtual ContextID comparators, n = 0-7 */
 #define TRCCIDCVRn(n)			(0x600 + (n * 8))
 #define TRCVMIDCVRn(n)			(0x640 + (n * 8))
 #define TRCCIDCCTLR0			0x680
-- 
2.24.1


WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mathieu.poirier@linaro.org, anshuman.khandual@arm.com,
	catalin.marinas@arm.com, coresight@lists.linaro.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-kernel@vger.kernel.org, leo.yan@linaro.org,
	jonathan.zhouwen@huawei.com, mike.leach@linaro.org
Subject: [PATCH v7 10/28] coresight: etm4x: Add commentary on the registers
Date: Sun, 10 Jan 2021 22:48:32 +0000	[thread overview]
Message-ID: <20210110224850.1880240-11-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210110224850.1880240-1-suzuki.poulose@arm.com>

As we are about define a switch..case table for individual register
access by offset for implementing the system instruction support,
document the possible set of registers for each group to make
it easier to correlate.

Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
Changes since v3
 - Fix commit description spelling mistake (Mathieu)
---
 drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++-------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index b6854f6fd666..3c2b49ffabc8 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -45,13 +45,13 @@
 #define TRCVDSACCTLR			0x0A4
 #define TRCVDARCCTLR			0x0A8
 /* Derived resources registers */
-#define TRCSEQEVRn(n)			(0x100 + (n * 4))
+#define TRCSEQEVRn(n)			(0x100 + (n * 4)) /* n = 0-2 */
 #define TRCSEQRSTEVR			0x118
 #define TRCSEQSTR			0x11C
 #define TRCEXTINSELR			0x120
-#define TRCCNTRLDVRn(n)			(0x140 + (n * 4))
-#define TRCCNTCTLRn(n)			(0x150 + (n * 4))
-#define TRCCNTVRn(n)			(0x160 + (n * 4))
+#define TRCCNTRLDVRn(n)			(0x140 + (n * 4)) /* n = 0-3 */
+#define TRCCNTCTLRn(n)			(0x150 + (n * 4)) /* n = 0-3 */
+#define TRCCNTVRn(n)			(0x160 + (n * 4)) /* n = 0-3 */
 /* ID registers */
 #define TRCIDR8				0x180
 #define TRCIDR9				0x184
@@ -60,7 +60,7 @@
 #define TRCIDR12			0x190
 #define TRCIDR13			0x194
 #define TRCIMSPEC0			0x1C0
-#define TRCIMSPECn(n)			(0x1C0 + (n * 4))
+#define TRCIMSPECn(n)			(0x1C0 + (n * 4)) /* n = 1-7 */
 #define TRCIDR0				0x1E0
 #define TRCIDR1				0x1E4
 #define TRCIDR2				0x1E8
@@ -69,9 +69,12 @@
 #define TRCIDR5				0x1F4
 #define TRCIDR6				0x1F8
 #define TRCIDR7				0x1FC
-/* Resource selection registers */
+/*
+ * Resource selection registers, n = 2-31.
+ * First pair (regs 0, 1) is always present and is reserved.
+ */
 #define TRCRSCTLRn(n)			(0x200 + (n * 4))
-/* Single-shot comparator registers */
+/* Single-shot comparator registers, n = 0-7 */
 #define TRCSSCCRn(n)			(0x280 + (n * 4))
 #define TRCSSCSRn(n)			(0x2A0 + (n * 4))
 #define TRCSSPCICRn(n)			(0x2C0 + (n * 4))
@@ -81,11 +84,13 @@
 #define TRCPDCR				0x310
 #define TRCPDSR				0x314
 /* Trace registers (0x318-0xEFC) */
-/* Comparator registers */
+/* Address Comparator registers n = 0-15 */
 #define TRCACVRn(n)			(0x400 + (n * 8))
 #define TRCACATRn(n)			(0x480 + (n * 8))
+/* Data Value Comparator Value registers, n = 0-7 */
 #define TRCDVCVRn(n)			(0x500 + (n * 16))
 #define TRCDVCMRn(n)			(0x580 + (n * 16))
+/* ContextID/Virtual ContextID comparators, n = 0-7 */
 #define TRCCIDCVRn(n)			(0x600 + (n * 8))
 #define TRCVMIDCVRn(n)			(0x640 + (n * 8))
 #define TRCCIDCCTLR0			0x680
-- 
2.24.1


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  parent reply	other threads:[~2021-01-10 22:52 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-10 22:48 [PATCH v7 00/28] coresight: etm4x: Support for system instructions Suzuki K Poulose
2021-01-10 22:48 ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 01/28] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 02/28] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-25 18:39   ` Mathieu Poirier
2021-01-25 18:39     ` Mathieu Poirier
2021-01-10 22:48 ` [PATCH v7 03/28] coresight: Introduce device access abstraction Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-25 18:42   ` Mathieu Poirier
2021-01-25 18:42     ` Mathieu Poirier
2021-01-10 22:48 ` [PATCH v7 04/28] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 05/28] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 06/28] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 07/28] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 08/28] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 09/28] coresight: etm4x: Make offset available for sysfs attributes Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` Suzuki K Poulose [this message]
2021-01-10 22:48   ` [PATCH v7 10/28] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 11/28] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 12/28] coresight: etm4x: Hide sysfs attributes for unavailable registers Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 13/28] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 14/28] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 15/28] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 16/28] coresight: etm4x: Clean up " Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 17/28] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 18/28] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 19/28] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 20/28] coresight: etm4x: Expose trcdevarch via sysfs Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 21/28] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 22/28] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 23/28] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 24/28] coresight: etm4x: Run arch feature detection on the CPU Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 25/28] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 26/28] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 27/28] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-01-10 22:48 ` [PATCH v7 28/28] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2021-01-10 22:48   ` Suzuki K Poulose
2021-02-12 10:34   ` Mike Leach
2021-02-12 10:34     ` Mike Leach
2021-02-12 15:36     ` Suzuki K Poulose
2021-02-12 15:36       ` Suzuki K Poulose
2021-02-12 17:30       ` Mike Leach
2021-02-12 17:30         ` Mike Leach
2021-02-18 14:51         ` Suzuki K Poulose
2021-02-18 14:51           ` Suzuki K Poulose
2021-01-25 18:49 ` [PATCH v7 00/28] coresight: etm4x: Support for system instructions Mathieu Poirier
2021-01-25 18:49   ` Mathieu Poirier
2021-01-25 22:05   ` Suzuki K Poulose
2021-01-25 22:05     ` Suzuki K Poulose

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