From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: coresight@lists.linaro.org, mathieu.poirier@linaro.org, anshuman.khandual@arm.com, mike.leach@linaro.org, leo.yan@linaro.org, linux-kernel@vger.kernel.org, jonathan.zhouwen@huawei.com, catalin.marinas@arm.com, Suzuki K Poulose <suzuki.poulose@arm.com> Subject: [PATCH v7 13/28] coresight: etm4x: Define DEVARCH register fields Date: Sun, 10 Jan 2021 22:48:35 +0000 [thread overview] Message-ID: <20210110224850.1880240-14-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210110224850.1880240-1-suzuki.poulose@arm.com> Define the fields of the DEVARCH register for identifying a component as an ETMv4.x unit. Going forward, we use the DEVARCH register for the component identification, rather than the TRCIDR3. Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- .../coresight/coresight-etm4x-core.c | 4 +- drivers/hwtracing/coresight/coresight-etm4x.h | 42 +++++++++++++++++++ 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index d8122b6284d9..043cd52a6fae 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1720,8 +1720,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) static struct amba_cs_uci_id uci_id_etm4[] = { { /* ETMv4 UCI data */ - .devarch = 0x47704a13, - .devarch_mask = 0xfff0ffff, + .devarch = ETM_DEVARCH_ETMv4x_ARCH, + .devarch_mask = ETM_DEVARCH_ID_MASK, .devtype = 0x00000013, } }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 193d2819afa7..fba3c02eea0b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -506,6 +506,48 @@ ETM_MODE_EXCL_KERN | \ ETM_MODE_EXCL_USER) +/* + * TRCDEVARCH Bit field definitions + * Bits[31:21] - ARCHITECT = Always Arm Ltd. + * * Bits[31:28] = 0x4 + * * Bits[27:21] = 0b0111011 + * Bit[20] - PRESENT, Indicates the presence of this register. + * + * Bit[19:16] - REVISION, Revision of the architecture. + * + * Bit[15:0] - ARCHID, Identifies this component as an ETM + * * Bits[15:12] - architecture version of ETM + * * = 4 for ETMv4 + * * Bits[11:0] = 0xA13, architecture part number for ETM. + */ +#define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21) +#define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21)) +#define ETM_DEVARCH_PRESENT BIT(20) +#define ETM_DEVARCH_REVISION_SHIFT 16 +#define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16) +#define ETM_DEVARCH_REVISION(x) \ + (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT) +#define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0) +#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12 +#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12) +#define ETM_DEVARCH_ARCHID_ARCH_VER(x) \ + (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) + +#define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \ + (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) + +#define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL) + +#define ETM_DEVARCH_MAKE_ARCHID(major) \ + ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13)) + +#define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4) + +#define ETM_DEVARCH_ID_MASK \ + (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT) +#define ETM_DEVARCH_ETMv4x_ARCH \ + (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT) + #define TRCSTATR_IDLE_BIT 0 #define TRCSTATR_PMSTABLE_BIT 1 #define ETM_DEFAULT_ADDR_COMP 0 -- 2.24.1
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: mathieu.poirier@linaro.org, anshuman.khandual@arm.com, catalin.marinas@arm.com, coresight@lists.linaro.org, Suzuki K Poulose <suzuki.poulose@arm.com>, linux-kernel@vger.kernel.org, leo.yan@linaro.org, jonathan.zhouwen@huawei.com, mike.leach@linaro.org Subject: [PATCH v7 13/28] coresight: etm4x: Define DEVARCH register fields Date: Sun, 10 Jan 2021 22:48:35 +0000 [thread overview] Message-ID: <20210110224850.1880240-14-suzuki.poulose@arm.com> (raw) In-Reply-To: <20210110224850.1880240-1-suzuki.poulose@arm.com> Define the fields of the DEVARCH register for identifying a component as an ETMv4.x unit. Going forward, we use the DEVARCH register for the component identification, rather than the TRCIDR3. Cc: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- .../coresight/coresight-etm4x-core.c | 4 +- drivers/hwtracing/coresight/coresight-etm4x.h | 42 +++++++++++++++++++ 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index d8122b6284d9..043cd52a6fae 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1720,8 +1720,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) static struct amba_cs_uci_id uci_id_etm4[] = { { /* ETMv4 UCI data */ - .devarch = 0x47704a13, - .devarch_mask = 0xfff0ffff, + .devarch = ETM_DEVARCH_ETMv4x_ARCH, + .devarch_mask = ETM_DEVARCH_ID_MASK, .devtype = 0x00000013, } }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 193d2819afa7..fba3c02eea0b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -506,6 +506,48 @@ ETM_MODE_EXCL_KERN | \ ETM_MODE_EXCL_USER) +/* + * TRCDEVARCH Bit field definitions + * Bits[31:21] - ARCHITECT = Always Arm Ltd. + * * Bits[31:28] = 0x4 + * * Bits[27:21] = 0b0111011 + * Bit[20] - PRESENT, Indicates the presence of this register. + * + * Bit[19:16] - REVISION, Revision of the architecture. + * + * Bit[15:0] - ARCHID, Identifies this component as an ETM + * * Bits[15:12] - architecture version of ETM + * * = 4 for ETMv4 + * * Bits[11:0] = 0xA13, architecture part number for ETM. + */ +#define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21) +#define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21)) +#define ETM_DEVARCH_PRESENT BIT(20) +#define ETM_DEVARCH_REVISION_SHIFT 16 +#define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16) +#define ETM_DEVARCH_REVISION(x) \ + (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT) +#define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0) +#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12 +#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12) +#define ETM_DEVARCH_ARCHID_ARCH_VER(x) \ + (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) + +#define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \ + (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) + +#define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL) + +#define ETM_DEVARCH_MAKE_ARCHID(major) \ + ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13)) + +#define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4) + +#define ETM_DEVARCH_ID_MASK \ + (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT) +#define ETM_DEVARCH_ETMv4x_ARCH \ + (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT) + #define TRCSTATR_IDLE_BIT 0 #define TRCSTATR_PMSTABLE_BIT 1 #define ETM_DEFAULT_ADDR_COMP 0 -- 2.24.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-10 22:50 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-10 22:48 [PATCH v7 00/28] coresight: etm4x: Support for system instructions Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 01/28] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 02/28] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-25 18:39 ` Mathieu Poirier 2021-01-25 18:39 ` Mathieu Poirier 2021-01-10 22:48 ` [PATCH v7 03/28] coresight: Introduce device access abstraction Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-25 18:42 ` Mathieu Poirier 2021-01-25 18:42 ` Mathieu Poirier 2021-01-10 22:48 ` [PATCH v7 04/28] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 05/28] coresight: Convert coresight_timeout to use " Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 06/28] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 07/28] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 08/28] coresight: etm4x: Convert all register accesses Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 09/28] coresight: etm4x: Make offset available for sysfs attributes Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 10/28] coresight: etm4x: Add commentary on the registers Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 11/28] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 12/28] coresight: etm4x: Hide sysfs attributes for unavailable registers Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose [this message] 2021-01-10 22:48 ` [PATCH v7 13/28] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 14/28] coresight: etm4x: Check for Software Lock Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 15/28] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 16/28] coresight: etm4x: Clean up " Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 17/28] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 18/28] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 19/28] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 20/28] coresight: etm4x: Expose trcdevarch via sysfs Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 21/28] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 22/28] coresight: etm4x: Detect system instructions support Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 23/28] coresight: etm4x: Refactor probing routine Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 24/28] coresight: etm4x: Run arch feature detection on the CPU Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 25/28] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 26/28] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 27/28] arm64: Add TRFCR_ELx definitions Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-01-10 22:48 ` [PATCH v7 28/28] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose 2021-01-10 22:48 ` Suzuki K Poulose 2021-02-12 10:34 ` Mike Leach 2021-02-12 10:34 ` Mike Leach 2021-02-12 15:36 ` Suzuki K Poulose 2021-02-12 15:36 ` Suzuki K Poulose 2021-02-12 17:30 ` Mike Leach 2021-02-12 17:30 ` Mike Leach 2021-02-18 14:51 ` Suzuki K Poulose 2021-02-18 14:51 ` Suzuki K Poulose 2021-01-25 18:49 ` [PATCH v7 00/28] coresight: etm4x: Support for system instructions Mathieu Poirier 2021-01-25 18:49 ` Mathieu Poirier 2021-01-25 22:05 ` Suzuki K Poulose 2021-01-25 22:05 ` Suzuki K Poulose
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210110224850.1880240-14-suzuki.poulose@arm.com \ --to=suzuki.poulose@arm.com \ --cc=anshuman.khandual@arm.com \ --cc=catalin.marinas@arm.com \ --cc=coresight@lists.linaro.org \ --cc=jonathan.zhouwen@huawei.com \ --cc=leo.yan@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=mathieu.poirier@linaro.org \ --cc=mike.leach@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.