From: Anshuman Gupta <anshuman.gupta@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jani.nikula@intel.com, Karthik B S <karthik.b.s@intel.com>, uma.shankar@intel.com, seanpaul@chromium.org, Anshuman Gupta <anshuman.gupta@intel.com>, juston.li@intel.com Subject: [PATCH v9 08/19] drm/i915/hdcp: Configure HDCP1.4 MST steram encryption status Date: Mon, 11 Jan 2021 13:41:09 +0530 [thread overview] Message-ID: <20210111081120.28417-9-anshuman.gupta@intel.com> (raw) In-Reply-To: <20210111081120.28417-1-anshuman.gupta@intel.com> Enable HDCP 1.4 DP MST stream encryption. Enable stream encryption once encryption is enabled on the DP transport driving the link for each stream which has requested encryption. Disable stream encryption for each stream that no longer requires encryption before disabling HDCP encryption on the link. v2: - Added debug print for stream encryption. - Disable the hdcp on port after disabling last stream encryption. v3: - Cosmetic change, removed the value less comment. [Uma] v4: - Split the Gen12 HDCP enablement patch. [Ram] - Add connector details in drm_err. v5: - uniformity for connector detail in DMESG. [Ram] - comments improvement. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Tested-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/display/intel_hdcp.c | 38 +++++++++++++++-------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 6e6465b4ecfa..fce444d69521 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -766,10 +766,17 @@ static int intel_hdcp_auth(struct intel_connector *connector) return -ETIMEDOUT; } - /* - * XXX: If we have MST-connected devices, we need to enable encryption - * on those as well. - */ + /* DP MST Auth Part 1 Step 2.a and Step 2.b */ + if (shim->stream_encryption) { + ret = shim->stream_encryption(connector, true); + if (ret) { + drm_err(&dev_priv->drm, "[%s:%d] Failed to enable HDCP 1.4 stream enc\n", + connector->base.name, connector->base.base.id); + return ret; + } + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", + transcoder_name(hdcp->stream_transcoder)); + } if (repeater_present) return intel_hdcp_auth_downstream(connector); @@ -791,18 +798,23 @@ static int _intel_hdcp_disable(struct intel_connector *connector) drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n", connector->base.name, connector->base.base.id); + if (hdcp->shim->stream_encryption) { + ret = hdcp->shim->stream_encryption(connector, false); + if (ret) { + drm_err(&dev_priv->drm, "[%s:%d] Failed to disable HDCP 1.4 stream enc\n", + connector->base.name, connector->base.base.id); + return ret; + } + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", + transcoder_name(hdcp->stream_transcoder)); + } + /* - * If there are other connectors on this port using HDCP, don't disable - * it. Instead, toggle the HDCP signalling off on that particular - * connector/pipe and exit. + * If there are other connectors on this port using HDCP, don't disable it + * until it disabled HDCP encryption for all connectors in MST topology. */ - if (dig_port->num_hdcp_streams > 0) { - ret = hdcp->shim->toggle_signalling(dig_port, - cpu_transcoder, false); - if (ret) - DRM_ERROR("Failed to disable HDCP signalling\n"); + if (dig_port->num_hdcp_streams > 0) return ret; - } hdcp->hdcp_encrypted = false; intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0); -- 2.26.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Gupta <anshuman.gupta@intel.com> To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: jani.nikula@intel.com, seanpaul@chromium.org Subject: [Intel-gfx] [PATCH v9 08/19] drm/i915/hdcp: Configure HDCP1.4 MST steram encryption status Date: Mon, 11 Jan 2021 13:41:09 +0530 [thread overview] Message-ID: <20210111081120.28417-9-anshuman.gupta@intel.com> (raw) In-Reply-To: <20210111081120.28417-1-anshuman.gupta@intel.com> Enable HDCP 1.4 DP MST stream encryption. Enable stream encryption once encryption is enabled on the DP transport driving the link for each stream which has requested encryption. Disable stream encryption for each stream that no longer requires encryption before disabling HDCP encryption on the link. v2: - Added debug print for stream encryption. - Disable the hdcp on port after disabling last stream encryption. v3: - Cosmetic change, removed the value less comment. [Uma] v4: - Split the Gen12 HDCP enablement patch. [Ram] - Add connector details in drm_err. v5: - uniformity for connector detail in DMESG. [Ram] - comments improvement. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Tested-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/display/intel_hdcp.c | 38 +++++++++++++++-------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 6e6465b4ecfa..fce444d69521 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -766,10 +766,17 @@ static int intel_hdcp_auth(struct intel_connector *connector) return -ETIMEDOUT; } - /* - * XXX: If we have MST-connected devices, we need to enable encryption - * on those as well. - */ + /* DP MST Auth Part 1 Step 2.a and Step 2.b */ + if (shim->stream_encryption) { + ret = shim->stream_encryption(connector, true); + if (ret) { + drm_err(&dev_priv->drm, "[%s:%d] Failed to enable HDCP 1.4 stream enc\n", + connector->base.name, connector->base.base.id); + return ret; + } + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", + transcoder_name(hdcp->stream_transcoder)); + } if (repeater_present) return intel_hdcp_auth_downstream(connector); @@ -791,18 +798,23 @@ static int _intel_hdcp_disable(struct intel_connector *connector) drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n", connector->base.name, connector->base.base.id); + if (hdcp->shim->stream_encryption) { + ret = hdcp->shim->stream_encryption(connector, false); + if (ret) { + drm_err(&dev_priv->drm, "[%s:%d] Failed to disable HDCP 1.4 stream enc\n", + connector->base.name, connector->base.base.id); + return ret; + } + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", + transcoder_name(hdcp->stream_transcoder)); + } + /* - * If there are other connectors on this port using HDCP, don't disable - * it. Instead, toggle the HDCP signalling off on that particular - * connector/pipe and exit. + * If there are other connectors on this port using HDCP, don't disable it + * until it disabled HDCP encryption for all connectors in MST topology. */ - if (dig_port->num_hdcp_streams > 0) { - ret = hdcp->shim->toggle_signalling(dig_port, - cpu_transcoder, false); - if (ret) - DRM_ERROR("Failed to disable HDCP signalling\n"); + if (dig_port->num_hdcp_streams > 0) return ret; - } hdcp->hdcp_encrypted = false; intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0); -- 2.26.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-01-11 8:26 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-11 8:11 [PATCH v9 00/19] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 01/19] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 02/19] drm/i915/hdcp: Get conn while content_type changed Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 03/19] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 04/19] drm/i915/hdcp: No HDCP when encoder is't initialized Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 05/19] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 06/19] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 07/19] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` Anshuman Gupta [this message] 2021-01-11 8:11 ` [Intel-gfx] [PATCH v9 08/19] drm/i915/hdcp: Configure HDCP1.4 MST steram encryption status Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 09/19] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 10/19] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 11/19] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 12/19] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 13/19] drm/hdcp: Max MST content streams Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 14/19] drm/i915/hdcp: MST streams support in hdcp port_data Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-12 5:26 ` Li, Juston 2021-01-12 5:26 ` [Intel-gfx] " Li, Juston 2021-01-11 8:11 ` [PATCH v9 15/19] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 16/19] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 17/19] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 18/19] drm/i915/hdcp: Configure HDCP2.2 MST steram encryption status Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:11 ` [PATCH v9 19/19] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta 2021-01-11 8:11 ` [Intel-gfx] " Anshuman Gupta 2021-01-11 8:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev9) Patchwork 2021-01-13 3:40 ` Gupta, Anshuman
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210111081120.28417-9-anshuman.gupta@intel.com \ --to=anshuman.gupta@intel.com \ --cc=dri-devel@lists.freedesktop.org \ --cc=intel-gfx@lists.freedesktop.org \ --cc=jani.nikula@intel.com \ --cc=juston.li@intel.com \ --cc=karthik.b.s@intel.com \ --cc=seanpaul@chromium.org \ --cc=uma.shankar@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.