From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> To: robdclark@gmail.com Cc: sean@poorly.run, airlied@linux.ie, daniel@ffwll.ch, jcrouse@codeaurora.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Subject: [PATCH v3 7/7] drm/msm/a5xx: Disable UCHE global filter Date: Wed, 13 Jan 2021 19:33:39 +0100 [thread overview] Message-ID: <20210113183339.446239-8-angelogioacchino.delregno@somainline.org> (raw) In-Reply-To: <20210113183339.446239-1-angelogioacchino.delregno@somainline.org> From: Konrad Dybcio <konrad.dybcio@somainline.org> Port over the command from downstream to prevent undefined behaviour. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> --- drivers/gpu/drm/msm/adreno/a5xx.xml.h | 2 ++ drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h index 346cc6ff3a36..7b9fcfe95c04 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h @@ -2367,6 +2367,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 +#define REG_A5XX_UCHE_MODE_CNTL 0x00000e81 + #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 23fc851756de..7e553d3efeb2 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -754,6 +754,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) adreno_is_a512(adreno_gpu)) gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); + /* Disable UCHE global filter as SP can invalidate/flush independently */ + gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29)); + /* Enable USE_RETENTION_FLOPS */ gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> To: robdclark@gmail.com Cc: freedreno@lists.freedesktop.org, airlied@linux.ie, linux-arm-msm@vger.kernel.org, konrad.dybcio@somainline.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, martin.botka@somainline.org, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>, marijn.suijten@somainline.org, phone-devel@vger.kernel.org, sean@poorly.run Subject: [PATCH v3 7/7] drm/msm/a5xx: Disable UCHE global filter Date: Wed, 13 Jan 2021 19:33:39 +0100 [thread overview] Message-ID: <20210113183339.446239-8-angelogioacchino.delregno@somainline.org> (raw) In-Reply-To: <20210113183339.446239-1-angelogioacchino.delregno@somainline.org> From: Konrad Dybcio <konrad.dybcio@somainline.org> Port over the command from downstream to prevent undefined behaviour. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> --- drivers/gpu/drm/msm/adreno/a5xx.xml.h | 2 ++ drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h index 346cc6ff3a36..7b9fcfe95c04 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h @@ -2367,6 +2367,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 +#define REG_A5XX_UCHE_MODE_CNTL 0x00000e81 + #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 23fc851756de..7e553d3efeb2 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -754,6 +754,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) adreno_is_a512(adreno_gpu)) gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); + /* Disable UCHE global filter as SP can invalidate/flush independently */ + gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29)); + /* Enable USE_RETENTION_FLOPS */ gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); -- 2.29.2 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2021-01-13 18:34 UTC|newest] Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-13 18:33 [PATCH v3 0/7] Add support for Adreno 508/509/512 AngeloGioacchino Del Regno 2021-01-13 18:33 ` AngeloGioacchino Del Regno 2021-01-13 18:33 ` [PATCH v3 1/7] drm/msm/a5xx: Remove overwriting A5XX_PC_DBG_ECO_CNTL register AngeloGioacchino Del Regno 2021-01-13 18:33 ` AngeloGioacchino Del Regno 2021-01-13 18:33 ` [PATCH v3 2/7] drm/msm/a5xx: Separate A5XX_PC_DBG_ECO_CNTL write from main branch AngeloGioacchino Del Regno 2021-01-13 18:33 ` AngeloGioacchino Del Regno 2021-01-13 18:33 ` [PATCH v3 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs AngeloGioacchino Del Regno 2021-01-13 18:33 ` AngeloGioacchino Del Regno 2021-01-13 18:33 ` [PATCH v3 4/7] drm/msm/a5xx: Reset VBIF before PC only on A510 and A530 AngeloGioacchino Del Regno 2021-01-13 18:33 ` AngeloGioacchino Del Regno 2021-01-13 18:33 ` [PATCH v3 5/7] drm/msm/a5xx: Fix VPC protect value in gpu_write() AngeloGioacchino Del Regno 2021-01-13 18:33 ` AngeloGioacchino Del Regno 2021-01-14 22:23 ` Jordan Crouse 2021-01-14 22:23 ` Jordan Crouse 2021-01-13 18:33 ` [PATCH v3 6/7] drm/msm/a5xx: Disable flat shading optimization AngeloGioacchino Del Regno 2021-01-13 18:33 ` AngeloGioacchino Del Regno 2021-01-14 22:24 ` Jordan Crouse 2021-01-14 22:24 ` Jordan Crouse 2021-01-13 18:33 ` AngeloGioacchino Del Regno [this message] 2021-01-13 18:33 ` [PATCH v3 7/7] drm/msm/a5xx: Disable UCHE global filter AngeloGioacchino Del Regno 2021-01-14 22:24 ` Jordan Crouse 2021-01-14 22:24 ` Jordan Crouse 2021-03-01 19:59 ` [PATCH v3 0/7] Add support for Adreno 508/509/512 patchwork-bot+linux-arm-msm
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210113183339.446239-8-angelogioacchino.delregno@somainline.org \ --to=angelogioacchino.delregno@somainline.org \ --cc=airlied@linux.ie \ --cc=daniel@ffwll.ch \ --cc=dri-devel@lists.freedesktop.org \ --cc=freedreno@lists.freedesktop.org \ --cc=jcrouse@codeaurora.org \ --cc=konrad.dybcio@somainline.org \ --cc=linux-arm-msm@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=marijn.suijten@somainline.org \ --cc=martin.botka@somainline.org \ --cc=phone-devel@vger.kernel.org \ --cc=robdclark@gmail.com \ --cc=sean@poorly.run \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.