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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start
Date: Wed, 13 Jan 2021 14:09:32 -0800	[thread overview]
Message-ID: <20210113220935.4151-16-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20210113220935.4151-1-manasi.d.navare@intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

With VRR the earliest the registers can get latched are at
flipline decision boundary, calculate that as vrr_vmin_vblank_start()
and the latest the regsiters can get latched are vmax decision boundary
calculate that as vrr_vmax_vblank_start()

Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 36 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  2 ++
 2 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5dc6d578760a..9a18c36e4a9a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -45,6 +45,42 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
 	}
 }
 
+/*
+ * Without VRR registers get latched at:
+ *  vblank_start
+ *
+ * With VRR the earliest registers can get latched is:
+ *  intel_vrr_vmin_vblank_start(), which if we want to maintain
+ *  the correct min vtotal is >=vblank_start+1
+ *
+ * The latest point registers can get latched is the vmax decision boundary:
+ *  intel_vrr_vmax_vblank_start()
+ *
+ * Between those two points the vblank exit starts (and hence registers get
+ * latched) ASAP after a push is sent.
+ *
+ * framestart_delay is programmable 0-3.
+ */
+static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+	/* TODO: Not sure why the hw imposes the extra scanline?, also check on TGL */
+	return crtc_state->vrr.pipeline_full + i915->framestart_delay + 2;
+}
+
+int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	/* Min vblank actually determined by flipline that is always >=vmin+1 */
+	return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
+}
+
+int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
+}
+
 void
 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			 struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 7610051edad2..d8b6b45557ca 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -27,5 +27,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
 void intel_vrr_get_config(struct intel_crtc *crtc,
 			  struct intel_crtc_state *crtc_state);
+int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
+int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.19.1

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  parent reply	other threads:[~2021-01-13 22:05 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-13 22:09 [Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 02/18] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-21 22:32   ` Navare, Manasi
2021-01-22 12:20     ` Ville Syrjälä
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-21 22:36   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-21 22:52   ` Navare, Manasi
2021-01-21 23:07     ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Manasi Navare
2021-01-14 17:15   ` Ville Syrjälä
2021-01-21 22:58     ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields Manasi Navare
2021-01-21 22:59   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 14/18] drm/i915/display: Add HW state readout for VRR Manasi Navare
2021-01-13 22:09 ` Manasi Navare [this message]
2021-01-19 19:07   ` [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start Ville Syrjälä
2021-01-21 23:00     ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-21 23:02   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-21 23:05   ` Navare, Manasi
2021-01-13 22:09 ` [Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-21 23:06   ` Navare, Manasi
2021-01-13 22:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+ Patchwork
2021-01-13 22:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-13 23:05 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-01-19 18:59 ` [Intel-gfx] [PATCH v4 00/18] " Ville Syrjälä

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