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From: Roger Pau Monne <roger.pau@citrix.com>
To: <xen-devel@lists.xenproject.org>
Cc: Roger Pau Monne <roger.pau@citrix.com>,
	Jan Beulich <jbeulich@suse.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>
Subject: [PATCH v2 1/4] x86/vioapic: check IRR before attempting to inject interrupt after EOI
Date: Fri, 15 Jan 2021 15:28:17 +0100	[thread overview]
Message-ID: <20210115142820.35224-2-roger.pau@citrix.com> (raw)
In-Reply-To: <20210115142820.35224-1-roger.pau@citrix.com>

In vioapic_update_EOI the irq_lock will be dropped in order to forward
the EOI to the dpci handler, so there's a window between clearing IRR
and checking if the line is asserted where IRR can change behind our
back.

Fix this by checking whether IRR is set before attempting to inject a
new interrupt.

Fixes: 06e3f8f2766 ('vt-d: Do dpci eoi outside of irq_lock.')
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/hvm/vioapic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c
index eb6c143f74..804bc77279 100644
--- a/xen/arch/x86/hvm/vioapic.c
+++ b/xen/arch/x86/hvm/vioapic.c
@@ -526,7 +526,7 @@ void vioapic_update_EOI(struct domain *d, u8 vector)
             }
 
             if ( (ent->fields.trig_mode == VIOAPIC_LEVEL_TRIG) &&
-                 !ent->fields.mask &&
+                 !ent->fields.mask && !ent->fields.remote_irr &&
                  hvm_irq->gsi_assert_count[vioapic->base_gsi + pin] )
             {
                 ent->fields.remote_irr = 1;
-- 
2.29.2



  reply	other threads:[~2021-01-15 14:29 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-15 14:28 [PATCH v2 0/4] x86/intr: guest interrupt handling fixes/cleanup Roger Pau Monne
2021-01-15 14:28 ` Roger Pau Monne [this message]
2021-01-21 16:03   ` [PATCH v2 1/4] x86/vioapic: check IRR before attempting to inject interrupt after EOI Jan Beulich
2021-01-21 17:27     ` Roger Pau Monné
2021-01-15 14:28 ` [PATCH v2 2/4] x86/vioapic: issue EOI to dpci when switching pin to edge trigger mode Roger Pau Monne
2021-01-21 16:23   ` Jan Beulich
2021-01-21 17:45     ` Roger Pau Monné
2021-01-22  9:13       ` Jan Beulich
2021-01-15 14:28 ` [PATCH v2 3/4] x86/vpic: issue dpci EOI for cleared pins at ICW1 Roger Pau Monne
2021-01-22  9:02   ` Jan Beulich
2021-01-22  9:53     ` Roger Pau Monné
2021-01-22 10:06       ` Jan Beulich
2021-01-15 14:28 ` [PATCH v2 4/4] x86/dpci: remove the dpci EOI timer Roger Pau Monne
2021-01-15 14:56   ` Roger Pau Monné
2021-01-22 11:37   ` Jan Beulich

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