From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 4/6] drm/i915/gt: Disable the ring before resetting HEAD/TAIL
Date: Tue, 19 Jan 2021 11:08:00 +0000 [thread overview]
Message-ID: <20210119110802.22228-4-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20210119110802.22228-1-chris@chris-wilson.co.uk>
During the reset of ring submission, we first stop the engine by
clearing the HEAD/TAIL and marking the ring as disabled. However, it
would be safer to disable the ring (after emptying) before resetting the
HEAD/TAIL.
Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 44159595d909..8a5314b97b04 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -301,13 +301,17 @@ static void xcs_sanitize(struct intel_engine_cs *engine)
static bool stop_ring(struct intel_engine_cs *engine)
{
+ /* Empty the ring by skipping to the end */
ENGINE_WRITE_FW(engine, RING_HEAD, ENGINE_READ_FW(engine, RING_TAIL));
-
- ENGINE_WRITE_FW(engine, RING_HEAD, 0);
- ENGINE_WRITE_FW(engine, RING_TAIL, 0);
+ ENGINE_POSTING_READ(engine, RING_HEAD);
/* The ring must be empty before it is disabled */
ENGINE_WRITE_FW(engine, RING_CTL, 0);
+ ENGINE_POSTING_READ(engine, RING_CTL);
+
+ /* Then reset the disabled ring */
+ ENGINE_WRITE_FW(engine, RING_HEAD, 0);
+ ENGINE_WRITE_FW(engine, RING_TAIL, 0);
return (ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) == 0;
}
--
2.20.1
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next prev parent reply other threads:[~2021-01-19 11:08 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-19 11:07 [Intel-gfx] [CI 1/6] drm/i915/gt: One more flush for Baytrail clear residuals Chris Wilson
2021-01-19 11:07 ` [Intel-gfx] [CI 2/6] drm/i915/selftests: Prepare the selftests for engine resets with ring submission Chris Wilson
2021-01-19 11:07 ` [Intel-gfx] [CI 3/6] drm/i915/gt: Lift stop_ring() to reset_prepare Chris Wilson
2021-01-19 11:08 ` Chris Wilson [this message]
2021-01-19 11:08 ` [Intel-gfx] [CI 4/6] drm/i915/gt: Disable the ring before resetting HEAD/TAIL Mika Kuoppala
2021-01-19 11:08 ` [Intel-gfx] [CI 5/6] drm/i915/gt: Pull ring submission resume under its caller forcewake Chris Wilson
2021-01-19 11:08 ` [Intel-gfx] [CI 6/6] drm/i915: Mark per-engine-reset as supported on gen7 Chris Wilson
2021-01-19 16:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/6] drm/i915/gt: One more flush for Baytrail clear residuals Patchwork
2021-01-19 16:30 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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