All of lore.kernel.org
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/33] target/arm: use arm_is_el2_enabled() where applicable
Date: Tue, 19 Jan 2021 15:10:37 +0000	[thread overview]
Message-ID: <20210119151104.16264-7-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210119151104.16264-1-peter.maydell@linaro.org>

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

Do not assume that EL2 is available in and only in non-secure context.
That equivalence is broken by ARMv8.4-SEL2.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-3-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h        |  4 ++--
 target/arm/helper-a64.c |  8 +-------
 target/arm/helper.c     | 33 +++++++++++++--------------------
 3 files changed, 16 insertions(+), 29 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0bdda90914a..66e36032949 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2210,7 +2210,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
         return aa64;
     }
 
-    if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
+    if (arm_is_el2_enabled(env)) {
         aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
     }
 
@@ -3154,7 +3154,7 @@ static inline int arm_debug_target_el(CPUARMState *env)
     bool secure = arm_is_secure(env);
     bool route_to_el2 = false;
 
-    if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
+    if (arm_is_el2_enabled(env)) {
         route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
                        env->cp15.mdcr_el2 & MDCR_TDE;
     }
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 30b2ad119f3..c426c23d2c4 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -972,8 +972,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
     if (new_el == -1) {
         goto illegal_return;
     }
-    if (new_el > cur_el
-        || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
+    if (new_el > cur_el || (new_el == 2 && !arm_is_el2_enabled(env))) {
         /* Disallow return to an EL which is unimplemented or higher
          * than the current one.
          */
@@ -985,11 +984,6 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
         goto illegal_return;
     }
 
-    if (new_el == 2 && arm_is_secure_below_el3(env)) {
-        /* Return to the non-existent secure-EL2 */
-        goto illegal_return;
-    }
-
     if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
         goto illegal_return;
     }
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b2ea93c4722..ae208ab00fa 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1049,8 +1049,8 @@ static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     if (arm_feature(env, ARM_FEATURE_V8)) {
         /* Check if CPACR accesses are to be trapped to EL2 */
-        if (arm_current_el(env) == 1 &&
-            (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
+        if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) &&
+            (env->cp15.cptr_el[2] & CPTR_TCPAC)) {
             return CP_ACCESS_TRAP_EL2;
         /* Check if CPACR accesses are to be trapped to EL3 */
         } else if (arm_current_el(env) < 3 &&
@@ -2520,7 +2520,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
                                         bool isread)
 {
     unsigned int cur_el = arm_current_el(env);
-    bool secure = arm_is_secure(env);
+    bool has_el2 = arm_is_el2_enabled(env);
     uint64_t hcr = arm_hcr_el2_eff(env);
 
     switch (cur_el) {
@@ -2544,8 +2544,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
             }
         } else {
             /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
-            if (arm_feature(env, ARM_FEATURE_EL2) &&
-                timeridx == GTIMER_PHYS && !secure &&
+            if (has_el2 && timeridx == GTIMER_PHYS &&
                 !extract32(env->cp15.cnthctl_el2, 1, 1)) {
                 return CP_ACCESS_TRAP_EL2;
             }
@@ -2554,8 +2553,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
 
     case 1:
         /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
-        if (arm_feature(env, ARM_FEATURE_EL2) &&
-            timeridx == GTIMER_PHYS && !secure &&
+        if (has_el2 && timeridx == GTIMER_PHYS &&
             (hcr & HCR_E2H
              ? !extract32(env->cp15.cnthctl_el2, 10, 1)
              : !extract32(env->cp15.cnthctl_el2, 0, 1))) {
@@ -2570,7 +2568,7 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
                                       bool isread)
 {
     unsigned int cur_el = arm_current_el(env);
-    bool secure = arm_is_secure(env);
+    bool has_el2 = arm_is_el2_enabled(env);
     uint64_t hcr = arm_hcr_el2_eff(env);
 
     switch (cur_el) {
@@ -2591,8 +2589,7 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
         /* fall through */
 
     case 1:
-        if (arm_feature(env, ARM_FEATURE_EL2) &&
-            timeridx == GTIMER_PHYS && !secure) {
+        if (has_el2 && timeridx == GTIMER_PHYS) {
             if (hcr & HCR_E2H) {
                 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
                 if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
@@ -4248,11 +4245,9 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
 
 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
-    ARMCPU *cpu = env_archcpu(env);
     unsigned int cur_el = arm_current_el(env);
-    bool secure = arm_is_secure(env);
 
-    if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
+    if (arm_is_el2_enabled(env) && cur_el == 1) {
         return env->cp15.vpidr_el2;
     }
     return raw_read(env, ri);
@@ -4279,9 +4274,8 @@ static uint64_t mpidr_read_val(CPUARMState *env)
 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     unsigned int cur_el = arm_current_el(env);
-    bool secure = arm_is_secure(env);
 
-    if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
+    if (arm_is_el2_enabled(env) && cur_el == 1) {
         return env->cp15.vmpidr_el2;
     }
     return mpidr_read_val(env);
@@ -5348,7 +5342,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
 {
     uint64_t ret = env->cp15.hcr_el2;
 
-    if (arm_is_secure_below_el3(env)) {
+    if (!arm_is_el2_enabled(env)) {
         /*
          * "This register has no effect if EL2 is not enabled in the
          * current Security state".  This is ARMv8.4-SecEL2 speak for
@@ -6145,7 +6139,7 @@ int sve_exception_el(CPUARMState *env, int el)
     /* CPTR_EL2.  Since TZ and TFP are positive,
      * they will be zero when EL2 is not present.
      */
-    if (el <= 2 && !arm_is_secure_below_el3(env)) {
+    if (el <= 2 && arm_is_el2_enabled(env)) {
         if (env->cp15.cptr_el[2] & CPTR_TZ) {
             return 2;
         }
@@ -8720,8 +8714,7 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
         }
         return 0;
     case ARM_CPU_MODE_HYP:
-        return !arm_feature(env, ARM_FEATURE_EL2)
-            || arm_current_el(env) < 2 || arm_is_secure_below_el3(env);
+        return !arm_is_el2_enabled(env) || arm_current_el(env) < 2;
     case ARM_CPU_MODE_MON:
         return arm_current_el(env) < 3;
     default:
@@ -12647,7 +12640,7 @@ int fp_exception_el(CPUARMState *env, int cur_el)
 
     /* CPTR_EL2 : present in v7VE or v8 */
     if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
-        && !arm_is_secure_below_el3(env)) {
+        && arm_is_el2_enabled(env)) {
         /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
         return 2;
     }
-- 
2.20.1



  parent reply	other threads:[~2021-01-19 15:23 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-19 15:10 [PULL 00/33] target-arm queue Peter Maydell
2021-01-19 15:10 ` [PULL 01/33] target/arm: Implement an IMPDEF pauth algorithm Peter Maydell
2021-01-19 15:10 ` [PULL 02/33] target/arm: Add cpu properties to control pauth Peter Maydell
2021-01-19 15:10 ` [PULL 03/33] target/arm: Use object_property_add_bool for "sve" property Peter Maydell
2021-01-19 15:10 ` [PULL 04/33] target/arm: remove redundant tests Peter Maydell
2021-01-19 15:10 ` [PULL 05/33] target/arm: add arm_is_el2_enabled() helper Peter Maydell
2021-01-19 15:10 ` Peter Maydell [this message]
2021-01-19 15:10 ` [PULL 07/33] target/arm: use arm_hcr_el2_eff() where applicable Peter Maydell
2021-01-19 15:10 ` [PULL 08/33] target/arm: factor MDCR_EL2 common handling Peter Maydell
2021-01-19 15:10 ` [PULL 09/33] target/arm: Define isar_feature function to test for presence of SEL2 Peter Maydell
2021-01-19 15:10 ` [PULL 10/33] target/arm: add 64-bit S-EL2 to EL exception table Peter Maydell
2021-01-19 15:10 ` [PULL 11/33] target/arm: add MMU stage 1 for Secure EL2 Peter Maydell
2021-01-19 15:10 ` [PULL 12/33] target/arm: add ARMv8.4-SEL2 system registers Peter Maydell
2021-01-19 15:10 ` [PULL 13/33] target/arm: handle VMID change in secure state Peter Maydell
2021-01-19 15:10 ` [PULL 14/33] target/arm: do S1_ptw_translate() before address space lookup Peter Maydell
2021-01-19 15:10 ` [PULL 15/33] target/arm: translate NS bit in page-walks Peter Maydell
2021-01-19 15:10 ` [PULL 16/33] target/arm: generalize 2-stage page-walk condition Peter Maydell
2021-01-19 15:10 ` [PULL 17/33] target/arm: secure stage 2 translation regime Peter Maydell
2021-01-19 15:10 ` [PULL 18/33] target/arm: set HPFAR_EL2.NS on secure stage 2 faults Peter Maydell
2021-01-19 15:10 ` [PULL 19/33] target/arm: revector to run-time pick target EL Peter Maydell
2021-01-19 15:10 ` [PULL 20/33] target/arm: Implement SCR_EL2.EEL2 Peter Maydell
2021-01-19 15:10 ` [PULL 21/33] target/arm: enable Secure EL2 in max CPU Peter Maydell
2021-01-19 15:10 ` [PULL 22/33] target/arm: refactor vae1_tlbmask() Peter Maydell
2021-01-19 15:10 ` [PULL 23/33] target/arm: Introduce PREDDESC field definitions Peter Maydell
2021-01-19 15:10 ` [PULL 24/33] target/arm: Update PFIRST, PNEXT for pred_desc Peter Maydell
2021-01-19 15:10 ` [PULL 25/33] target/arm: Update ZIP, UZP, TRN " Peter Maydell
2021-01-19 15:10 ` [PULL 26/33] target/arm: Update REV, PUNPK " Peter Maydell
2021-01-19 15:10 ` [PULL 27/33] hw/misc/pvpanic: split-out generic and bus dependent code Peter Maydell
2021-01-19 15:10 ` [PULL 28/33] hw/misc/pvpanic: add PCI interface support Peter Maydell
2021-01-19 15:11 ` [PULL 29/33] pvpanic : update pvpanic spec document Peter Maydell
2021-01-19 15:11 ` [PULL 30/33] tests/qtest: add a test case for pvpanic-pci Peter Maydell
2021-01-19 15:11 ` [PULL 31/33] npcm7xx_adc-test: Fix memleak in adc_qom_set Peter Maydell
2021-01-19 15:11 ` [PULL 32/33] target/arm/m_helper: Silence GCC 10 maybe-uninitialized error Peter Maydell
2021-01-19 15:11 ` [PULL 33/33] docs: Build and install all the docs in a single manual Peter Maydell
2021-01-19 16:00 ` [PULL 00/33] target-arm queue no-reply

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210119151104.16264-7-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.