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From: Michael Tretter <m.tretter@pengutronix.de>
To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Cc: m.mtretter@pengutronix.de, michals@xilinx.com,
	kernel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org
Subject: [PATCH v3 02/15] clk: divider: fix initialization with parent_hw
Date: Thu, 21 Jan 2021 08:16:46 +0100	[thread overview]
Message-ID: <20210121071659.1226489-3-m.tretter@pengutronix.de> (raw)
In-Reply-To: <20210121071659.1226489-1-m.tretter@pengutronix.de>

If a driver registers a divider clock with a parent_hw instead of the
parent_name, the parent_hw is ignored and the clock does not have a
parent.

Fix this by initializing the parents the same way they are initialized
for clock gates.

Fixes: ff258817137a ("clk: divider: Add support for specifying parents via DT/pointers")
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
---
Changelog:

v3: none

v2:
- Add fixes tag
---
 drivers/clk/clk-divider.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c499799693cc..344997203f0e 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -494,8 +494,13 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
 	else
 		init.ops = &clk_divider_ops;
 	init.flags = flags;
-	init.parent_names = (parent_name ? &parent_name: NULL);
-	init.num_parents = (parent_name ? 1 : 0);
+	init.parent_names = parent_name ? &parent_name : NULL;
+	init.parent_hws = parent_hw ? &parent_hw : NULL;
+	init.parent_data = parent_data;
+	if (parent_name || parent_hw || parent_data)
+		init.num_parents = 1;
+	else
+		init.num_parents = 0;
 
 	/* struct clk_divider assignments */
 	div->reg = reg;
-- 
2.20.1


WARNING: multiple messages have this Message-ID (diff)
From: Michael Tretter <m.tretter@pengutronix.de>
To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Cc: sboyd@kernel.org, mturquette@baylibre.com,
	m.mtretter@pengutronix.de, michals@xilinx.com,
	kernel@pengutronix.de
Subject: [PATCH v3 02/15] clk: divider: fix initialization with parent_hw
Date: Thu, 21 Jan 2021 08:16:46 +0100	[thread overview]
Message-ID: <20210121071659.1226489-3-m.tretter@pengutronix.de> (raw)
In-Reply-To: <20210121071659.1226489-1-m.tretter@pengutronix.de>

If a driver registers a divider clock with a parent_hw instead of the
parent_name, the parent_hw is ignored and the clock does not have a
parent.

Fix this by initializing the parents the same way they are initialized
for clock gates.

Fixes: ff258817137a ("clk: divider: Add support for specifying parents via DT/pointers")
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
---
Changelog:

v3: none

v2:
- Add fixes tag
---
 drivers/clk/clk-divider.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c499799693cc..344997203f0e 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -494,8 +494,13 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
 	else
 		init.ops = &clk_divider_ops;
 	init.flags = flags;
-	init.parent_names = (parent_name ? &parent_name: NULL);
-	init.num_parents = (parent_name ? 1 : 0);
+	init.parent_names = parent_name ? &parent_name : NULL;
+	init.parent_hws = parent_hw ? &parent_hw : NULL;
+	init.parent_data = parent_data;
+	if (parent_name || parent_hw || parent_data)
+		init.num_parents = 1;
+	else
+		init.num_parents = 0;
 
 	/* struct clk_divider assignments */
 	div->reg = reg;
-- 
2.20.1


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  parent reply	other threads:[~2021-01-21  7:19 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-21  7:16 [PATCH v3 00/15] soc: xilinx: vcu: Convert driver to clock provider Michael Tretter
2021-01-21  7:16 ` Michael Tretter
2021-01-21  7:16 ` [PATCH v3 01/15] ARM: dts: vcu: define indexes for output clocks Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:32   ` Stephen Boyd
2021-02-09  2:32     ` Stephen Boyd
2021-01-21  7:16 ` Michael Tretter [this message]
2021-01-21  7:16   ` [PATCH v3 02/15] clk: divider: fix initialization with parent_hw Michael Tretter
2021-02-09  2:32   ` Stephen Boyd
2021-02-09  2:32     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 03/15] soc: xilinx: vcu: drop coreclk from struct xlnx_vcu Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:32   ` Stephen Boyd
2021-02-09  2:32     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 04/15] soc: xilinx: vcu: add helper to wait for PLL locked Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:32   ` Stephen Boyd
2021-02-09  2:32     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 05/15] soc: xilinx: vcu: add helpers for configuring PLL Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:32   ` Stephen Boyd
2021-02-09  2:32     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 06/15] soc: xilinx: vcu: implement PLL disable Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:32   ` Stephen Boyd
2021-02-09  2:32     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 07/15] soc: xilinx: vcu: register PLL as fixed rate clock Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:32   ` Stephen Boyd
2021-02-09  2:32     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 08/15] soc: xilinx: vcu: implement clock provider for output clocks Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:35   ` Stephen Boyd
2021-02-09  2:35     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 09/15] soc: xilinx: vcu: make pll post divider explicit Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:35   ` Stephen Boyd
2021-02-09  2:35     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 10/15] soc: xilinx: vcu: make the PLL configurable Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:35   ` Stephen Boyd
2021-02-09  2:35     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 11/15] soc: xilinx: vcu: remove calculation of PLL configuration Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:35   ` Stephen Boyd
2021-02-09  2:35     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 12/15] soc: xilinx: vcu: use bitfields for register definition Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:35   ` Stephen Boyd
2021-02-09  2:35     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 13/15] soc: xilinx: vcu: fix repeated word the in comment Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:35   ` Stephen Boyd
2021-02-09  2:35     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 14/15] soc: xilinx: vcu: fix alignment to open parenthesis Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:35   ` Stephen Boyd
2021-02-09  2:35     ` Stephen Boyd
2021-01-21  7:16 ` [PATCH v3 15/15] clk: xilinx: move xlnx_vcu clock driver from soc Michael Tretter
2021-01-21  7:16   ` Michael Tretter
2021-02-09  2:35   ` Stephen Boyd
2021-02-09  2:35     ` Stephen Boyd

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