From: Jean-Philippe Brucker <jean-philippe@linaro.org> To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>, vivek.gautam@arm.com, iommu@lists.linux-foundation.org, zhangfei.gao@linaro.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/3] iommu/arm-smmu-v3: TLB invalidation for SVA Date: Fri, 22 Jan 2021 12:52:55 +0100 [thread overview] Message-ID: <20210122115257.2502526-1-jean-philippe@linaro.org> (raw) To support sharing page tables with the CPU, the SMMU can participate in Broadcast TLB Maintenance (BTM), where TLB invalidate instructions from the CPU are received by the SMMU. For platforms that do no implement BTM [1], it is still possible to use SVA, by sending all TLB invalidations through the command queue. Patch 2 implements this. This series also enables SVA for platforms that do support BTM, as an intermediate step because properly supporting BTM requires cooperating with KVM to allocate VMIDs [2]. With BTM enabled, the SMMU applies broadcast invalidations by VMID to any matching TLB entry, because there is no distinction between private and shared VMIDs like there is for ASIDs. Therefore a stage-2 domain will need a VMID that doesn't conflict with one allocated by KVM (or use the one from the corresponding VM, pinned). These patches, along with the IOPF series [3] and the quirks [4], enable SVA for the hisi accelerator that's already supported upstream. My quick performance comparison between BTM and !BTM on that platform were inconclusive. Doing invalidations via cmdq seemed to slightly reduce performance of some heavy compression jobs, but there was too much noise and not enough invalidations in my tests. This series does not depend on the IOPF one [3]. [1] https://lore.kernel.org/linux-iommu/BY5PR12MB37641E84D516054387FEE330B3CC0@BY5PR12MB3764.namprd12.prod.outlook.com/ [2] https://lore.kernel.org/linux-iommu/20200522101755.GA3453945@myrica/ [3] https://lore.kernel.org/linux-iommu/20210121123623.2060416-1-jean-philippe@linaro.org/ [4] https://lore.kernel.org/linux-pci/1610960316-28935-1-git-send-email-zhangfei.gao@linaro.org/ Jean-Philippe Brucker (3): iommu/arm-smmu-v3: Split arm_smmu_tlb_inv_range() iommu/arm-smmu-v3: Make BTM optional for SVA iommu/arm-smmu-v3: Add support for VHE drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 + .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 14 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 104 ++++++++++++------ 3 files changed, 89 insertions(+), 35 deletions(-) -- 2.30.0 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Jean-Philippe Brucker <jean-philippe@linaro.org> To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>, vivek.gautam@arm.com, eric.auger@redhat.com, iommu@lists.linux-foundation.org, Jonathan.Cameron@huawei.com, zhangfei.gao@linaro.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 0/3] iommu/arm-smmu-v3: TLB invalidation for SVA Date: Fri, 22 Jan 2021 12:52:55 +0100 [thread overview] Message-ID: <20210122115257.2502526-1-jean-philippe@linaro.org> (raw) To support sharing page tables with the CPU, the SMMU can participate in Broadcast TLB Maintenance (BTM), where TLB invalidate instructions from the CPU are received by the SMMU. For platforms that do no implement BTM [1], it is still possible to use SVA, by sending all TLB invalidations through the command queue. Patch 2 implements this. This series also enables SVA for platforms that do support BTM, as an intermediate step because properly supporting BTM requires cooperating with KVM to allocate VMIDs [2]. With BTM enabled, the SMMU applies broadcast invalidations by VMID to any matching TLB entry, because there is no distinction between private and shared VMIDs like there is for ASIDs. Therefore a stage-2 domain will need a VMID that doesn't conflict with one allocated by KVM (or use the one from the corresponding VM, pinned). These patches, along with the IOPF series [3] and the quirks [4], enable SVA for the hisi accelerator that's already supported upstream. My quick performance comparison between BTM and !BTM on that platform were inconclusive. Doing invalidations via cmdq seemed to slightly reduce performance of some heavy compression jobs, but there was too much noise and not enough invalidations in my tests. This series does not depend on the IOPF one [3]. [1] https://lore.kernel.org/linux-iommu/BY5PR12MB37641E84D516054387FEE330B3CC0@BY5PR12MB3764.namprd12.prod.outlook.com/ [2] https://lore.kernel.org/linux-iommu/20200522101755.GA3453945@myrica/ [3] https://lore.kernel.org/linux-iommu/20210121123623.2060416-1-jean-philippe@linaro.org/ [4] https://lore.kernel.org/linux-pci/1610960316-28935-1-git-send-email-zhangfei.gao@linaro.org/ Jean-Philippe Brucker (3): iommu/arm-smmu-v3: Split arm_smmu_tlb_inv_range() iommu/arm-smmu-v3: Make BTM optional for SVA iommu/arm-smmu-v3: Add support for VHE drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 + .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 14 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 104 ++++++++++++------ 3 files changed, 89 insertions(+), 35 deletions(-) -- 2.30.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2021-01-22 11:56 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-01-22 11:52 Jean-Philippe Brucker [this message] 2021-01-22 11:52 ` [PATCH 0/3] iommu/arm-smmu-v3: TLB invalidation for SVA Jean-Philippe Brucker 2021-01-22 11:52 ` [PATCH 1/3] iommu/arm-smmu-v3: Split arm_smmu_tlb_inv_range() Jean-Philippe Brucker 2021-01-22 11:52 ` Jean-Philippe Brucker 2021-01-22 13:49 ` Will Deacon 2021-01-22 13:49 ` Will Deacon 2021-01-22 13:56 ` Robin Murphy 2021-01-22 13:56 ` Robin Murphy 2021-01-22 11:52 ` [PATCH 2/3] iommu/arm-smmu-v3: Make BTM optional for SVA Jean-Philippe Brucker 2021-01-22 11:52 ` Jean-Philippe Brucker 2021-01-22 14:04 ` Robin Murphy 2021-01-22 14:04 ` Robin Murphy 2021-01-22 14:13 ` Jean-Philippe Brucker 2021-01-22 14:13 ` Jean-Philippe Brucker 2021-01-22 11:52 ` [PATCH 3/3] iommu/arm-smmu-v3: Add support for VHE Jean-Philippe Brucker 2021-01-22 11:52 ` Jean-Philippe Brucker 2021-01-22 13:29 ` [PATCH 0/3] iommu/arm-smmu-v3: TLB invalidation for SVA Jonathan Cameron 2021-01-22 13:29 ` Jonathan Cameron
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210122115257.2502526-1-jean-philippe@linaro.org \ --to=jean-philippe@linaro.org \ --cc=iommu@lists.linux-foundation.org \ --cc=joro@8bytes.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=robin.murphy@arm.com \ --cc=vivek.gautam@arm.com \ --cc=will@kernel.org \ --cc=zhangfei.gao@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.