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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH 03/10] drm/i915/gt: Remove repeated words from comments
Date: Fri, 22 Jan 2021 15:06:15 +0000	[thread overview]
Message-ID: <20210122150622.21088-3-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20210122150622.21088-1-chris@chris-wilson.co.uk>

Checkpatch spotted a few repeated words in the comment, genuine
mistakes.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
 drivers/gpu/drm/i915/gt/intel_ggtt.c                 | 2 +-
 drivers/gpu/drm/i915/gt/intel_reset_types.h          | 2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c          | 2 +-
 drivers/gpu/drm/i915/gt/selftest_execlists.c         | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 3e680bfa9d13..304d4b8e08e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3108,7 +3108,7 @@ static void execlists_release(struct intel_engine_cs *engine)
 static void
 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
 {
-	/* Default vfuncs which can be overriden by each engine. */
+	/* Default vfuncs which can be overridden by each engine. */
 
 	engine->resume = execlists_resume;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index eece0844fbe9..dac07d66f658 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -92,7 +92,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *i915)
 }
 
 /*
- * Certain Gen5 chipsets require require idling the GPU before
+ * Certain Gen5 chipsets require idling the GPU before
  * unmapping anything from the GTT when VT-d is enabled.
  */
 static bool needs_idle_maps(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset_types.h b/drivers/gpu/drm/i915/gt/intel_reset_types.h
index add6b86d9d03..9312b29f5a97 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset_types.h
@@ -32,7 +32,7 @@ struct intel_reset {
 	 *
 	 * #I915_WEDGED_ON_INIT - If we fail to initialize the GPU we can no
 	 * longer use the GPU - similar to #I915_WEDGED bit. The difference in
-	 * in the way we're handling "forced" unwedged (e.g. through debugfs),
+	 * the way we're handling "forced" unwedged (e.g. through debugfs),
 	 * which is not allowed in case we failed to initialize.
 	 *
 	 * #I915_WEDGED_ON_FINI - Similar to #I915_WEDGED_ON_INIT, except we
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e51e6977016a..8abfd6ad9718 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -280,7 +280,7 @@ static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
 		     PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
 	/* Use Force Non-Coherent whenever executing a 3D context. This is a
-	 * workaround for for a possible hang in the unlikely event a TLB
+	 * workaround for a possible hang in the unlikely event a TLB
 	 * invalidation occurs during a PSD flush.
 	 */
 	/* WaForceEnableNonCoherent:bdw,chv */
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 4f2853a83075..6cfa9a89d891 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -2864,7 +2864,7 @@ static int __live_preempt_ring(struct intel_engine_cs *engine,
 	err = wait_for_submit(engine, rq, HZ / 2);
 	i915_request_put(rq);
 	if (err) {
-		pr_err("%s: preemption request was not submited\n",
+		pr_err("%s: preemption request was not submitted\n",
 		       engine->name);
 		err = -ETIME;
 	}
-- 
2.20.1

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  parent reply	other threads:[~2021-01-22 15:06 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-22 15:06 [Intel-gfx] [PATCH 01/10] drm/i915/gt: SPDX cleanup Chris Wilson
2021-01-22 15:06 ` [Intel-gfx] [PATCH 02/10] drm/i915/gt: Add some missing blank lines after declaration Chris Wilson
2021-01-22 15:06 ` Chris Wilson [this message]
2021-01-22 15:06 ` [Intel-gfx] [PATCH 04/10] drm/i915/gt: Fixup misaligned function parameters Chris Wilson
2021-01-22 15:06 ` [Intel-gfx] [PATCH 05/10] drm/i915/gt: Remove a bonus newline Chris Wilson
2021-01-22 15:06 ` [Intel-gfx] [PATCH 06/10] drm/i915/gt: Wrap macro arg in () Chris Wilson
2021-01-22 15:06 ` [Intel-gfx] [PATCH 07/10] drm/i915/gt: Insert spaces into GEN3_L3LOG_SIZE/4 Chris Wilson
2021-01-22 15:06 ` [Intel-gfx] [PATCH 08/10] drm/i915/gt: Replace unnecessary ',' with '; ' Chris Wilson
2021-01-22 15:06 ` [Intel-gfx] [PATCH 09/10] drm/i915/gt: Add a space before '(' Chris Wilson
2021-01-22 15:06 ` [Intel-gfx] [PATCH 10/10] drm/i915/gt: Replace 'return' with a fall-through Chris Wilson
2021-01-22 15:43 ` [Intel-gfx] [PATCH 01/10] drm/i915/gt: SPDX cleanup Michal Wajdeczko
2021-01-22 15:49   ` Chris Wilson
2021-01-22 16:03     ` Michal Wajdeczko
2021-01-22 16:16       ` Chris Wilson
2021-01-22 18:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] " Patchwork
2021-01-22 18:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-22 19:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-23  3:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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