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From: Rebecca Cran <rebecca@nuviainc.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Rebecca Cran <rebecca@nuviainc.com>,
	Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v3 1/4] target/arm: Remove PSTATE_SS from cpsr and move it into env->pstate.
Date: Wed, 27 Jan 2021 21:45:26 -0700	[thread overview]
Message-ID: <20210128044529.1403-2-rebecca@nuviainc.com> (raw)
In-Reply-To: <20210128044529.1403-1-rebecca@nuviainc.com>

cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
 target/arm/helper-a64.c | 2 +-
 target/arm/helper.c     | 2 +-
 target/arm/op_helper.c  | 9 +--------
 3 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index c426c23d2c4e..a6b162049806 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -1001,7 +1001,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
         mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
         cpsr_write(env, spsr, mask, CPSRWriteRaw);
         if (!arm_singlestep_active(env)) {
-            env->uncached_cpsr &= ~PSTATE_SS;
+            env->pstate &= ~PSTATE_SS;
         }
         aarch64_sync_64_to_32(env);
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2ead3fcbdbd..7b7e72ba878c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9402,7 +9402,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
      * For exceptions taken to AArch32 we must clear the SS bit in both
      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
      */
-    env->uncached_cpsr &= ~PSTATE_SS;
+    env->pstate &= ~PSTATE_SS;
     env->spsr = cpsr_read(env);
     /* Clear IT bits.  */
     env->condexec_bits = 0;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 5e0f123043b5..65cb37d088f8 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -389,14 +389,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
 
 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 {
-    /*
-     * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr.
-     * This is convenient for populating SPSR_ELx, but must be
-     * hidden from aarch32 mode, where it is not visible.
-     *
-     * TODO: ARMv8.4-DIT -- need to move SS somewhere else.
-     */
-    return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS);
+    return cpsr_read(env) & ~CPSR_EXEC;
 }
 
 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
-- 
2.26.2



  reply	other threads:[~2021-01-28  4:46 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-28  4:45 [PATCH v3 0/4] target/arm: Add support for FEAT_DIT, Data Independent Timing Rebecca Cran
2021-01-28  4:45 ` Rebecca Cran [this message]
2021-01-28  5:00   ` [PATCH v3 1/4] target/arm: Remove PSTATE_SS from cpsr and move it into env->pstate Richard Henderson
2021-01-28  4:45 ` [PATCH v3 2/4] target/arm: Add support for FEAT_DIT, Data Independent Timing Rebecca Cran
2021-01-28  5:06   ` Richard Henderson
2021-02-02 22:21     ` Rebecca Cran
2021-02-03  0:11       ` Richard Henderson
2021-01-28  4:45 ` [PATCH v3 3/4] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU Rebecca Cran
2021-01-28  4:45 ` [PATCH v3 4/4] target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU Rebecca Cran
2021-01-28  5:07   ` Richard Henderson

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