From: Aditya Swarup <aditya.swarup@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 7/8] drm/i915/adl_s: Add display WAs for ADL-S
Date: Fri, 29 Jan 2021 10:29:44 -0800 [thread overview]
Message-ID: <20210129182945.217078-8-aditya.swarup@intel.com> (raw)
In-Reply-To: <20210129182945.217078-1-aditya.swarup@intel.com>
- Extend permanent driver WA Wa_1409767108, Wa_14010685332
and Wa_14011294188 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s.
- Add Wa_14011765242 for adl-s A0 stepping.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++--
drivers/gpu/drm/i915/intel_device_info.c | 6 +++++-
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cccfd45a67cf..e17b1ca356c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5339,9 +5339,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
int config, i;
- if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+ if (IS_ALDERLAKE_S(dev_priv) ||
+ IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
- /* Wa_1409767108:tgl,dg1 */
+ /* Wa_1409767108:tgl,dg1,adl-s */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
@@ -5379,7 +5380,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* Wa_14011294188:ehl,jsl,tgl,rkl */
+ /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index b1c7e9b010f4..402030251c64 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2392,8 +2392,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- /* Wa_1606054188:tgl */
- if (IS_TIGERLAKE(dev_priv) &&
+ /* Wa_1606054188:tgl,adl-s */
+ if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
intel_format_is_p01x(fb->format->format)) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 85d6883745d8..92ad3e7d1f6f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -250,7 +250,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
enum pipe pipe;
- if (INTEL_GEN(dev_priv) >= 10) {
+ /* Wa_14011765242: adl-s A0 */
+ if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0))
+ for_each_pipe(dev_priv, pipe)
+ runtime->num_scalers[pipe] = 0;
+ else if (INTEL_GEN(dev_priv) >= 10) {
for_each_pipe(dev_priv, pipe)
runtime->num_scalers[pipe] = 2;
} else if (IS_GEN(dev_priv, 9)) {
--
2.27.0
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next prev parent reply other threads:[~2021-01-29 18:30 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-29 18:29 [Intel-gfx] [PATCH 0/8] Final set of patches for ADLS enabling Aditya Swarup
2021-01-29 18:29 ` [Intel-gfx] [PATCH 1/8] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2021-01-29 18:29 ` [Intel-gfx] [PATCH 2/8] drm/i915/adl_s: Add power wells Aditya Swarup
2021-01-29 18:29 ` [Intel-gfx] [PATCH 3/8] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2021-01-29 18:29 ` [Intel-gfx] [PATCH 4/8] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
2021-01-29 18:29 ` [Intel-gfx] [PATCH 5/8] drm/i915/adl_s: Load DMC Aditya Swarup
2021-01-29 18:29 ` [Intel-gfx] [PATCH 6/8] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2021-01-29 18:29 ` Aditya Swarup [this message]
2021-01-29 18:54 ` [Intel-gfx] [PATCH 7/8] drm/i915/adl_s: Add display WAs for ADL-S Souza, Jose
2021-01-29 18:29 ` [Intel-gfx] [PATCH 8/8] drm/i915/adl_s: Add GT and CTX " Aditya Swarup
2021-01-29 19:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Final set of patches for ADLS enabling (rev3) Patchwork
2021-01-29 19:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-29 19:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-30 1:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-01-30 17:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Final set of patches for ADLS enabling (rev4) Patchwork
2021-01-30 17:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-30 17:40 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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