From: Alexandre Belloni <alexandre.belloni@bootlin.com> To: Arnd Bergmann <arnd@arndb.de>, soc@kernel.org Cc: Vladimir Zapolskiy <vz@mleia.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandre Belloni <alexandre.belloni@bootlin.com>, Gregory CLEMENT <gregory.clement@bootlin.com> Subject: [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL Date: Wed, 3 Feb 2021 10:03:20 +0100 [thread overview] Message-ID: <20210203090320.GA3760268@piout.net> (raw) This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7. The lpc32xx clock driver is not able to actually change the PLL rate as this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK, then stop the PLL, update the register, restart the PLL and wait for the PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK PLL. Currently, the HCLK driver simply updates the registers but this has no real effect and all the clock rate calculation end up being wrong. This is especially annoying for the peripheral (e.g. UARTs, I2C, SPI). Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- Arnd, This is a very important fix that was sent back in may and october 2019 without any reply from the maintainers, please consider applying it so it can be backported on v5.10. arch/arm/boot/dts/lpc32xx.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 3a5cfb0ddb20..c87066d6c995 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -326,9 +326,6 @@ clk: clock-controller@0 { clocks = <&xtal_32k>, <&xtal>; clock-names = "xtal_32k", "xtal"; - - assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>; - assigned-clock-rates = <208000000>; }; }; -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Belloni <alexandre.belloni@bootlin.com> To: Arnd Bergmann <arnd@arndb.de>, soc@kernel.org Cc: Gregory CLEMENT <gregory.clement@bootlin.com>, Alexandre Belloni <alexandre.belloni@bootlin.com>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Vladimir Zapolskiy <vz@mleia.com> Subject: [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL Date: Wed, 3 Feb 2021 10:03:20 +0100 [thread overview] Message-ID: <20210203090320.GA3760268@piout.net> (raw) Message-ID: <20210203090320.C5fmvYmBpg_f0ELuJ_-H--1n7O4hi68IXDKbnA3g68Y@z> (raw) This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7. The lpc32xx clock driver is not able to actually change the PLL rate as this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK, then stop the PLL, update the register, restart the PLL and wait for the PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK PLL. Currently, the HCLK driver simply updates the registers but this has no real effect and all the clock rate calculation end up being wrong. This is especially annoying for the peripheral (e.g. UARTs, I2C, SPI). Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- Arnd, This is a very important fix that was sent back in may and october 2019 without any reply from the maintainers, please consider applying it so it can be backported on v5.10. arch/arm/boot/dts/lpc32xx.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 3a5cfb0ddb20..c87066d6c995 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -326,9 +326,6 @@ clk: clock-controller@0 { clocks = <&xtal_32k>, <&xtal>; clock-names = "xtal_32k", "xtal"; - - assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>; - assigned-clock-rates = <208000000>; }; }; -- 2.29.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2021-02-03 9:05 UTC|newest] Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-02-03 9:03 Alexandre Belloni [this message] 2021-02-03 9:03 ` [PATCH RESEND v2] ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL Alexandre Belloni 2021-02-03 12:10 ` patchwork-bot+linux-soc 2021-02-03 12:31 ` Arnd Bergmann 2021-02-03 12:31 ` Arnd Bergmann -- strict thread matches above, loose matches on Subject: below -- 2021-01-04 0:43 Alexandre Belloni 2021-01-04 0:43 ` Alexandre Belloni
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