[Intel-gfx] [PATCH v3 01/15] drm/i915: Use intel_ddi_clk_select() for FDI

[Ville Syrjala <ville.syrjala@linux.intel.com>]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We want to put all DDI clock routing code into one place.
Unify the FDI enable sequence to use the standard function
instead of hand rolling its own. The disable sequence already
uses the normal thing.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_ddi.h | 3 ++-
 drivers/gpu/drm/i915/display/intel_fdi.c | 7 +++----
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 28877a31adc0..dbef228555a0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -184,7 +184,7 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 			port_name(port));
 }
 
-u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
+static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 {
 	switch (pll->info->id) {
 	case DPLL_ID_WRPLL1:
@@ -1845,8 +1845,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
 }
 
-static void intel_ddi_clk_select(struct intel_encoder *encoder,
-				 const struct intel_crtc_state *crtc_state)
+void intel_ddi_clk_select(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index f9a916cad7e7..e618e1c80252 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -28,7 +28,8 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
 				struct intel_encoder *intel_encoder,
 				const struct intel_crtc_state *old_crtc_state,
 				const struct drm_connector_state *old_conn_state);
-u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll);
+void intel_ddi_clk_select(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state);
 void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state);
 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 77df675e607e..dbd6be3342c0 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -565,7 +565,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 temp, i, rx_ctl_val, ddi_pll_sel;
+	u32 temp, i, rx_ctl_val;
 	int n_entries;
 
 	intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries);
@@ -595,9 +595,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
 
 	/* Configure Port Clock Select */
-	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
-	intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
-	drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
+	drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
+	intel_ddi_clk_select(encoder, crtc_state);
 
 	/* Start the training iterating through available voltages and emphasis,
 	 * testing each value twice. */
-- 
2.26.2

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