From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
Date: Fri, 12 Feb 2021 23:02:36 +0800 [thread overview]
Message-ID: <20210212150256.885-19-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 19 ++
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans/trans_rvp.c.inc | 20 ++
target/riscv/packed_helper.c | 268 ++++++++++++++++++++++++
4 files changed, 326 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 25aa07a7ff..b1f831bb02 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1294,3 +1294,22 @@ DEF_HELPER_4(kmmawb2, tl, env, tl, tl, tl)
DEF_HELPER_4(kmmawb2_u, tl, env, tl, tl, tl)
DEF_HELPER_4(kmmawt2, tl, env, tl, tl, tl)
DEF_HELPER_4(kmmawt2_u, tl, env, tl, tl, tl)
+
+DEF_HELPER_3(smbb16, tl, env, tl, tl)
+DEF_HELPER_3(smbt16, tl, env, tl, tl)
+DEF_HELPER_3(smtt16, tl, env, tl, tl)
+DEF_HELPER_3(kmda, tl, env, tl, tl)
+DEF_HELPER_3(kmxda, tl, env, tl, tl)
+DEF_HELPER_3(smds, tl, env, tl, tl)
+DEF_HELPER_3(smdrs, tl, env, tl, tl)
+DEF_HELPER_3(smxds, tl, env, tl, tl)
+DEF_HELPER_4(kmabb, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmabt, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmatt, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmada, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmaxda, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmads, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmadrs, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmaxds, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmsda, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmsxda, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6e63bab2d9..4e5cdbb928 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -762,3 +762,22 @@ kmmawb2 1100111 ..... ..... 001 ..... 1111111 @r
kmmawb2_u 1101111 ..... ..... 001 ..... 1111111 @r
kmmawt2 1110111 ..... ..... 001 ..... 1111111 @r
kmmawt2_u 1111111 ..... ..... 001 ..... 1111111 @r
+
+smbb16 0000100 ..... ..... 001 ..... 1111111 @r
+smbt16 0001100 ..... ..... 001 ..... 1111111 @r
+smtt16 0010100 ..... ..... 001 ..... 1111111 @r
+kmda 0011100 ..... ..... 001 ..... 1111111 @r
+kmxda 0011101 ..... ..... 001 ..... 1111111 @r
+smds 0101100 ..... ..... 001 ..... 1111111 @r
+smdrs 0110100 ..... ..... 001 ..... 1111111 @r
+smxds 0111100 ..... ..... 001 ..... 1111111 @r
+kmabb 0101101 ..... ..... 001 ..... 1111111 @r
+kmabt 0110101 ..... ..... 001 ..... 1111111 @r
+kmatt 0111101 ..... ..... 001 ..... 1111111 @r
+kmada 0100100 ..... ..... 001 ..... 1111111 @r
+kmaxda 0100101 ..... ..... 001 ..... 1111111 @r
+kmads 0101110 ..... ..... 001 ..... 1111111 @r
+kmadrs 0110110 ..... ..... 001 ..... 1111111 @r
+kmaxds 0111110 ..... ..... 001 ..... 1111111 @r
+kmsda 0100110 ..... ..... 001 ..... 1111111 @r
+kmsxda 0100111 ..... ..... 001 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index e708ae7a6a..261aab402a 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -582,3 +582,23 @@ GEN_RVP_R_ACC_OOL(kmmawb2);
GEN_RVP_R_ACC_OOL(kmmawb2_u);
GEN_RVP_R_ACC_OOL(kmmawt2);
GEN_RVP_R_ACC_OOL(kmmawt2_u);
+
+/* Signed 16-bit Multiply with 32-bit Add/Subtract Instructions */
+GEN_RVP_R_OOL(smbb16);
+GEN_RVP_R_OOL(smbt16);
+GEN_RVP_R_OOL(smtt16);
+GEN_RVP_R_OOL(kmda);
+GEN_RVP_R_OOL(kmxda);
+GEN_RVP_R_OOL(smds);
+GEN_RVP_R_OOL(smdrs);
+GEN_RVP_R_OOL(smxds);
+GEN_RVP_R_ACC_OOL(kmabb);
+GEN_RVP_R_ACC_OOL(kmabt);
+GEN_RVP_R_ACC_OOL(kmatt);
+GEN_RVP_R_ACC_OOL(kmada);
+GEN_RVP_R_ACC_OOL(kmaxda);
+GEN_RVP_R_ACC_OOL(kmads);
+GEN_RVP_R_ACC_OOL(kmadrs);
+GEN_RVP_R_ACC_OOL(kmaxds);
+GEN_RVP_R_ACC_OOL(kmsda);
+GEN_RVP_R_ACC_OOL(kmsxda);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index ea3c9f6dd8..b3673a33ee 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -1685,3 +1685,271 @@ static inline void do_kmmawt2_u(CPURISCVState *env, void *vd, void *va,
}
RVPR_ACC(kmmawt2_u, 1, 4);
+
+/* Signed 16-bit Multiply with 32-bit Add/Subtract Instruction */
+static inline void do_smbb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+}
+
+RVPR(smbb16, 1, 4);
+
+static inline void do_smbt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+}
+
+RVPR(smbt16, 1, 4);
+
+static inline void do_smtt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+}
+
+RVPR(smtt16, 1, 4);
+
+static inline void do_kmda(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ if (a[H2(2 * i)] == INT16_MIN && a[H2(2 * i + 1)] == INT16_MIN &&
+ b[H2(2 * i)] == INT16_MIN && a[H2(2 * i + 1)] == INT16_MIN) {
+ d[H4(i)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i)] = (int32_t)a[H2(2 * i)] * b[H2(2 * i)] +
+ (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+ }
+}
+
+RVPR(kmda, 1, 4);
+
+static inline void do_kmxda(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ if (a[H2(2 * i)] == INT16_MIN && a[H2(2 * i + 1)] == INT16_MIN &&
+ b[H2(2 * i)] == INT16_MIN && a[H2(2 * i + 1)] == INT16_MIN) {
+ d[H4(i)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i)] = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i)] +
+ (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+ }
+}
+
+RVPR(kmxda, 1, 4);
+
+static inline void do_smds(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)] -
+ (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+}
+
+RVPR(smds, 1, 4);
+
+static inline void do_smdrs(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i)] * b[H2(2 * i)] -
+ (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+}
+
+RVPR(smdrs, 1, 4);
+
+static inline void do_smxds(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i)] -
+ (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+}
+
+RVPR(smxds, 1, 4);
+
+static inline void do_kmabb(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = sadd32(env, 0, (int32_t)a[H2(2 * i)] * b[H2(2 * i)], c[H4(i)]);
+}
+
+RVPR_ACC(kmabb, 1, 4);
+
+static inline void do_kmabt(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = sadd32(env, 0, (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)],
+ c[H4(i)]);
+}
+
+RVPR_ACC(kmabt, 1, 4);
+
+static inline void do_kmatt(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = sadd32(env, 0, (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)],
+ c[H4(i)]);
+}
+
+RVPR_ACC(kmatt, 1, 4);
+
+static inline void do_kmada(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+ p2 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+
+ if (a[H2(i)] == INT16_MIN && a[H2(i + 1)] == INT16_MIN &&
+ b[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ if (c[H4(i)] < 0) {
+ d[H4(i)] = INT32_MAX + c[H4(i)] + 1ll;
+ } else {
+ env->vxsat = 0x1;
+ d[H4(i)] = INT32_MAX;
+ }
+ } else {
+ d[H4(i)] = sadd32(env, 0, p1 + p2, c[H4(i)]);
+ }
+}
+
+RVPR_ACC(kmada, 1, 4);
+
+static inline void do_kmaxda(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i)];
+ p2 = (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+
+ if (a[H2(2 * i)] == INT16_MIN && a[H2(2 * i + 1)] == INT16_MIN &&
+ b[H2(2 * i)] == INT16_MIN && b[H2(2 * i + 1)] == INT16_MIN) {
+ if (c[H4(i)] < 0) {
+ d[H4(i)] = INT32_MAX + c[H4(i)] + 1ll;
+ } else {
+ env->vxsat = 0x1;
+ d[H4(i)] = INT32_MAX;
+ }
+ } else {
+ d[H4(i)] = sadd32(env, 0, p1 + p2, c[H4(i)]);
+ }
+}
+
+RVPR_ACC(kmaxda, 1, 4);
+
+static inline void do_kmads(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+ p2 = (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+
+ d[H4(i)] = sadd32(env, 0, p1 - p2, c[H4(i)]);
+}
+
+RVPR_ACC(kmads, 1, 4);
+
+static inline void do_kmadrs(CPURISCVState *env, void *vd, void *va,
+ void *vb, void * vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+ p2 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+
+ d[H4(i)] = sadd32(env, 0, p1 - p2, c[H4(i)]);
+}
+
+RVPR_ACC(kmadrs, 1, 4);
+
+static inline void do_kmaxds(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i)];
+ p2 = (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+
+ d[H4(i)] = sadd32(env, 0, p1 - p2, c[H4(i)]);
+}
+
+RVPR_ACC(kmaxds, 1, 4);
+
+static inline void do_kmsda(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+ p2 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+
+ if (a[H2(i)] == INT16_MIN && a[H2(i + 1)] == INT16_MIN &&
+ b[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ if (c[H4(i)] < 0) {
+ env->vxsat = 0x1;
+ d[H4(i)] = INT32_MIN;
+ } else {
+ d[H4(i)] = c[H4(i)] - 1ll - INT32_MAX;
+ }
+ } else {
+ d[H4(i)] = ssub32(env, 0, c[H4(i)], p1 + p2);
+ }
+}
+
+RVPR_ACC(kmsda, 1, 4);
+
+static inline void do_kmsxda(CPURISCVState *env, void *vd, void *va,
+ void *vb, void * vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+ p2 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i)];
+
+ if (a[H2(i)] == INT16_MIN && a[H2(i + 1)] == INT16_MIN &&
+ b[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ if (d[H4(i)] < 0) {
+ env->vxsat = 0x1;
+ d[H4(i)] = INT32_MIN;
+ } else {
+ d[H4(i)] = c[H4(i)] - 1ll - INT32_MAX;
+ }
+ } else {
+ d[H4(i)] = ssub32(env, 0, c[H4(i)], p1 + p2);
+ }
+}
+
+RVPR_ACC(kmsxda, 1, 4);
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org,
alistair23@gmail.com, palmer@dabbelt.com,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
Date: Fri, 12 Feb 2021 23:02:36 +0800 [thread overview]
Message-ID: <20210212150256.885-19-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 19 ++
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans/trans_rvp.c.inc | 20 ++
target/riscv/packed_helper.c | 268 ++++++++++++++++++++++++
4 files changed, 326 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 25aa07a7ff..b1f831bb02 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1294,3 +1294,22 @@ DEF_HELPER_4(kmmawb2, tl, env, tl, tl, tl)
DEF_HELPER_4(kmmawb2_u, tl, env, tl, tl, tl)
DEF_HELPER_4(kmmawt2, tl, env, tl, tl, tl)
DEF_HELPER_4(kmmawt2_u, tl, env, tl, tl, tl)
+
+DEF_HELPER_3(smbb16, tl, env, tl, tl)
+DEF_HELPER_3(smbt16, tl, env, tl, tl)
+DEF_HELPER_3(smtt16, tl, env, tl, tl)
+DEF_HELPER_3(kmda, tl, env, tl, tl)
+DEF_HELPER_3(kmxda, tl, env, tl, tl)
+DEF_HELPER_3(smds, tl, env, tl, tl)
+DEF_HELPER_3(smdrs, tl, env, tl, tl)
+DEF_HELPER_3(smxds, tl, env, tl, tl)
+DEF_HELPER_4(kmabb, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmabt, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmatt, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmada, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmaxda, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmads, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmadrs, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmaxds, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmsda, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmsxda, tl, env, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6e63bab2d9..4e5cdbb928 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -762,3 +762,22 @@ kmmawb2 1100111 ..... ..... 001 ..... 1111111 @r
kmmawb2_u 1101111 ..... ..... 001 ..... 1111111 @r
kmmawt2 1110111 ..... ..... 001 ..... 1111111 @r
kmmawt2_u 1111111 ..... ..... 001 ..... 1111111 @r
+
+smbb16 0000100 ..... ..... 001 ..... 1111111 @r
+smbt16 0001100 ..... ..... 001 ..... 1111111 @r
+smtt16 0010100 ..... ..... 001 ..... 1111111 @r
+kmda 0011100 ..... ..... 001 ..... 1111111 @r
+kmxda 0011101 ..... ..... 001 ..... 1111111 @r
+smds 0101100 ..... ..... 001 ..... 1111111 @r
+smdrs 0110100 ..... ..... 001 ..... 1111111 @r
+smxds 0111100 ..... ..... 001 ..... 1111111 @r
+kmabb 0101101 ..... ..... 001 ..... 1111111 @r
+kmabt 0110101 ..... ..... 001 ..... 1111111 @r
+kmatt 0111101 ..... ..... 001 ..... 1111111 @r
+kmada 0100100 ..... ..... 001 ..... 1111111 @r
+kmaxda 0100101 ..... ..... 001 ..... 1111111 @r
+kmads 0101110 ..... ..... 001 ..... 1111111 @r
+kmadrs 0110110 ..... ..... 001 ..... 1111111 @r
+kmaxds 0111110 ..... ..... 001 ..... 1111111 @r
+kmsda 0100110 ..... ..... 001 ..... 1111111 @r
+kmsxda 0100111 ..... ..... 001 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index e708ae7a6a..261aab402a 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -582,3 +582,23 @@ GEN_RVP_R_ACC_OOL(kmmawb2);
GEN_RVP_R_ACC_OOL(kmmawb2_u);
GEN_RVP_R_ACC_OOL(kmmawt2);
GEN_RVP_R_ACC_OOL(kmmawt2_u);
+
+/* Signed 16-bit Multiply with 32-bit Add/Subtract Instructions */
+GEN_RVP_R_OOL(smbb16);
+GEN_RVP_R_OOL(smbt16);
+GEN_RVP_R_OOL(smtt16);
+GEN_RVP_R_OOL(kmda);
+GEN_RVP_R_OOL(kmxda);
+GEN_RVP_R_OOL(smds);
+GEN_RVP_R_OOL(smdrs);
+GEN_RVP_R_OOL(smxds);
+GEN_RVP_R_ACC_OOL(kmabb);
+GEN_RVP_R_ACC_OOL(kmabt);
+GEN_RVP_R_ACC_OOL(kmatt);
+GEN_RVP_R_ACC_OOL(kmada);
+GEN_RVP_R_ACC_OOL(kmaxda);
+GEN_RVP_R_ACC_OOL(kmads);
+GEN_RVP_R_ACC_OOL(kmadrs);
+GEN_RVP_R_ACC_OOL(kmaxds);
+GEN_RVP_R_ACC_OOL(kmsda);
+GEN_RVP_R_ACC_OOL(kmsxda);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index ea3c9f6dd8..b3673a33ee 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -1685,3 +1685,271 @@ static inline void do_kmmawt2_u(CPURISCVState *env, void *vd, void *va,
}
RVPR_ACC(kmmawt2_u, 1, 4);
+
+/* Signed 16-bit Multiply with 32-bit Add/Subtract Instruction */
+static inline void do_smbb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+}
+
+RVPR(smbb16, 1, 4);
+
+static inline void do_smbt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+}
+
+RVPR(smbt16, 1, 4);
+
+static inline void do_smtt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+}
+
+RVPR(smtt16, 1, 4);
+
+static inline void do_kmda(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ if (a[H2(2 * i)] == INT16_MIN && a[H2(2 * i + 1)] == INT16_MIN &&
+ b[H2(2 * i)] == INT16_MIN && a[H2(2 * i + 1)] == INT16_MIN) {
+ d[H4(i)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i)] = (int32_t)a[H2(2 * i)] * b[H2(2 * i)] +
+ (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+ }
+}
+
+RVPR(kmda, 1, 4);
+
+static inline void do_kmxda(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ if (a[H2(2 * i)] == INT16_MIN && a[H2(2 * i + 1)] == INT16_MIN &&
+ b[H2(2 * i)] == INT16_MIN && a[H2(2 * i + 1)] == INT16_MIN) {
+ d[H4(i)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i)] = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i)] +
+ (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+ }
+}
+
+RVPR(kmxda, 1, 4);
+
+static inline void do_smds(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)] -
+ (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+}
+
+RVPR(smds, 1, 4);
+
+static inline void do_smdrs(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i)] * b[H2(2 * i)] -
+ (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+}
+
+RVPR(smdrs, 1, 4);
+
+static inline void do_smxds(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i)] -
+ (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+}
+
+RVPR(smxds, 1, 4);
+
+static inline void do_kmabb(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = sadd32(env, 0, (int32_t)a[H2(2 * i)] * b[H2(2 * i)], c[H4(i)]);
+}
+
+RVPR_ACC(kmabb, 1, 4);
+
+static inline void do_kmabt(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = sadd32(env, 0, (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)],
+ c[H4(i)]);
+}
+
+RVPR_ACC(kmabt, 1, 4);
+
+static inline void do_kmatt(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ d[H4(i)] = sadd32(env, 0, (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)],
+ c[H4(i)]);
+}
+
+RVPR_ACC(kmatt, 1, 4);
+
+static inline void do_kmada(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+ p2 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+
+ if (a[H2(i)] == INT16_MIN && a[H2(i + 1)] == INT16_MIN &&
+ b[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ if (c[H4(i)] < 0) {
+ d[H4(i)] = INT32_MAX + c[H4(i)] + 1ll;
+ } else {
+ env->vxsat = 0x1;
+ d[H4(i)] = INT32_MAX;
+ }
+ } else {
+ d[H4(i)] = sadd32(env, 0, p1 + p2, c[H4(i)]);
+ }
+}
+
+RVPR_ACC(kmada, 1, 4);
+
+static inline void do_kmaxda(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i)];
+ p2 = (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+
+ if (a[H2(2 * i)] == INT16_MIN && a[H2(2 * i + 1)] == INT16_MIN &&
+ b[H2(2 * i)] == INT16_MIN && b[H2(2 * i + 1)] == INT16_MIN) {
+ if (c[H4(i)] < 0) {
+ d[H4(i)] = INT32_MAX + c[H4(i)] + 1ll;
+ } else {
+ env->vxsat = 0x1;
+ d[H4(i)] = INT32_MAX;
+ }
+ } else {
+ d[H4(i)] = sadd32(env, 0, p1 + p2, c[H4(i)]);
+ }
+}
+
+RVPR_ACC(kmaxda, 1, 4);
+
+static inline void do_kmads(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+ p2 = (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+
+ d[H4(i)] = sadd32(env, 0, p1 - p2, c[H4(i)]);
+}
+
+RVPR_ACC(kmads, 1, 4);
+
+static inline void do_kmadrs(CPURISCVState *env, void *vd, void *va,
+ void *vb, void * vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+ p2 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+
+ d[H4(i)] = sadd32(env, 0, p1 - p2, c[H4(i)]);
+}
+
+RVPR_ACC(kmadrs, 1, 4);
+
+static inline void do_kmaxds(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i)];
+ p2 = (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+
+ d[H4(i)] = sadd32(env, 0, p1 - p2, c[H4(i)]);
+}
+
+RVPR_ACC(kmaxds, 1, 4);
+
+static inline void do_kmsda(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i)] * b[H2(2 * i)];
+ p2 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i + 1)];
+
+ if (a[H2(i)] == INT16_MIN && a[H2(i + 1)] == INT16_MIN &&
+ b[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ if (c[H4(i)] < 0) {
+ env->vxsat = 0x1;
+ d[H4(i)] = INT32_MIN;
+ } else {
+ d[H4(i)] = c[H4(i)] - 1ll - INT32_MAX;
+ }
+ } else {
+ d[H4(i)] = ssub32(env, 0, c[H4(i)], p1 + p2);
+ }
+}
+
+RVPR_ACC(kmsda, 1, 4);
+
+static inline void do_kmsxda(CPURISCVState *env, void *vd, void *va,
+ void *vb, void * vc, uint8_t i)
+{
+ int32_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+ int32_t p1, p2;
+ p1 = (int32_t)a[H2(2 * i)] * b[H2(2 * i + 1)];
+ p2 = (int32_t)a[H2(2 * i + 1)] * b[H2(2 * i)];
+
+ if (a[H2(i)] == INT16_MIN && a[H2(i + 1)] == INT16_MIN &&
+ b[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ if (d[H4(i)] < 0) {
+ env->vxsat = 0x1;
+ d[H4(i)] = INT32_MIN;
+ } else {
+ d[H4(i)] = c[H4(i)] - 1ll - INT32_MAX;
+ }
+ } else {
+ d[H4(i)] = ssub32(env, 0, c[H4(i)], p1 + p2);
+ }
+}
+
+RVPR_ACC(kmsxda, 1, 4);
--
2.17.1
next prev parent reply other threads:[~2021-02-12 15:45 UTC|newest]
Thread overview: 150+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-09 14:08 ` Alistair Francis
2021-03-09 14:08 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-09 14:10 ` Alistair Francis
2021-03-09 14:10 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 18:52 ` Richard Henderson
2021-02-12 18:52 ` Richard Henderson
2021-03-09 14:11 ` Alistair Francis
2021-03-09 14:11 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 18:03 ` Richard Henderson
2021-02-12 18:03 ` Richard Henderson
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 16:20 ` Richard Henderson
2021-02-18 16:20 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 16:21 ` Richard Henderson
2021-02-18 16:21 ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:22 ` Alistair Francis
2021-03-15 21:22 ` Alistair Francis
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 6:15 ` Palmer Dabbelt
2021-05-26 6:15 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:25 ` Alistair Francis
2021-03-15 21:25 ` Alistair Francis
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 19:54 ` Alistair Francis
2021-03-16 19:54 ` Alistair Francis
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 20:39 ` Alistair Francis
2021-03-17 20:39 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:27 ` Alistair Francis
2021-03-15 21:27 ` Alistair Francis
2021-05-24 4:46 ` Palmer Dabbelt
2021-05-24 4:46 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:28 ` Alistair Francis
2021-03-15 21:28 ` Alistair Francis
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:31 ` Alistair Francis
2021-03-15 21:31 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:33 ` Alistair Francis
2021-03-15 21:33 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:35 ` Alistair Francis
2021-03-15 21:35 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-16 14:38 ` Alistair Francis
2021-03-16 14:38 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-16 14:40 ` Alistair Francis
2021-03-16 14:40 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-16 14:42 ` Alistair Francis
2021-03-16 14:42 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-16 16:01 ` Alistair Francis
2021-03-16 16:01 ` Alistair Francis
2021-02-12 15:02 ` LIU Zhiwei [this message]
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-16 19:44 ` Alistair Francis
2021-03-16 19:44 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-05 6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-03-05 6:14 ` LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-15 4:46 ` Alistair Francis
2021-04-15 4:46 ` Alistair Francis
2021-04-15 5:50 ` LIU Zhiwei
2021-04-15 5:50 ` LIU Zhiwei
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