From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
Date: Fri, 12 Feb 2021 23:02:50 +0800 [thread overview]
Message-ID: <20210212150256.885-33-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 10 ++
target/riscv/insn32-64.decode | 10 ++
target/riscv/insn_trans/trans_rvp.c.inc | 11 ++
target/riscv/packed_helper.c | 141 ++++++++++++++++++++++++
4 files changed, 172 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 384b42ce90..f8521a5388 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1440,4 +1440,14 @@ DEF_HELPER_3(umin32, tl, env, tl, tl)
DEF_HELPER_3(smax32, tl, env, tl, tl)
DEF_HELPER_3(umax32, tl, env, tl, tl)
DEF_HELPER_2(kabs32, tl, env, tl)
+
+DEF_HELPER_3(khmbb16, tl, env, tl, tl)
+DEF_HELPER_3(khmbt16, tl, env, tl, tl)
+DEF_HELPER_3(khmtt16, tl, env, tl, tl)
+DEF_HELPER_3(kdmbb16, tl, env, tl, tl)
+DEF_HELPER_3(kdmbt16, tl, env, tl, tl)
+DEF_HELPER_3(kdmtt16, tl, env, tl, tl)
+DEF_HELPER_4(kdmabb16, tl, env, tl, tl, tl)
+DEF_HELPER_4(kdmabt16, tl, env, tl, tl, tl)
+DEF_HELPER_4(kdmatt16, tl, env, tl, tl, tl)
#endif
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index a2b8831467..2e1c1817e4 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -135,3 +135,13 @@ umin32 1010000 ..... ..... 010 ..... 1111111 @r
smax32 1001001 ..... ..... 010 ..... 1111111 @r
umax32 1010001 ..... ..... 010 ..... 1111111 @r
kabs32 1010110 10010 ..... 000 ..... 1111111 @r2
+
+khmbb16 1101110 ..... ..... 001 ..... 1111111 @r
+khmbt16 1110110 ..... ..... 001 ..... 1111111 @r
+khmtt16 1111110 ..... ..... 001 ..... 1111111 @r
+kdmbb16 1101101 ..... ..... 001 ..... 1111111 @r
+kdmbt16 1110101 ..... ..... 001 ..... 1111111 @r
+kdmtt16 1111101 ..... ..... 001 ..... 1111111 @r
+kdmabb16 1101100 ..... ..... 001 ..... 1111111 @r
+kdmabt16 1110100 ..... ..... 001 ..... 1111111 @r
+kdmatt16 1111100 ..... ..... 001 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index ce144ee5c0..2b4418abd8 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1179,4 +1179,15 @@ GEN_RVP_R_OOL(umin32);
GEN_RVP_R_OOL(smax32);
GEN_RVP_R_OOL(umax32);
GEN_RVP_R2_OOL(kabs32);
+
+/* (RV64 Only) SIMD Q15 saturating Multiply Instructions */
+GEN_RVP_R_OOL(khmbb16);
+GEN_RVP_R_OOL(khmbt16);
+GEN_RVP_R_OOL(khmtt16);
+GEN_RVP_R_OOL(kdmbb16);
+GEN_RVP_R_OOL(kdmbt16);
+GEN_RVP_R_OOL(kdmtt16);
+GEN_RVP_R_ACC_OOL(kdmabb16);
+GEN_RVP_R_ACC_OOL(kdmabt16);
+GEN_RVP_R_ACC_OOL(kdmatt16);
#endif
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index c8a92f5b7d..5636848aaf 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3432,4 +3432,145 @@ static inline void do_kabs32(CPURISCVState *env, void *vd, void *va, uint8_t i)
}
RVPR2(kabs32, 1, 4);
+
+/* (RV64 Only) SIMD Q15 saturating Multiply Instructions */
+static inline void do_khmbb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ d[H4(i / 2)] = sat64(env, (int64_t)a[H2(i)] * b[H2(i)] >> 15, 15);
+}
+
+RVPR(khmbb16, 2, 2);
+
+static inline void do_khmbt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ d[H4(i / 2)] = sat64(env, (int64_t)a[H2(i)] * b[H2(i + 1)] >> 15, 15);
+}
+
+RVPR(khmbt16, 2, 2);
+
+static inline void do_khmtt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ d[H4(i / 2)] = sat64(env, (int64_t)a[H2(i + 1)] * b[H2(i + 1)] >> 15, 15);
+}
+
+RVPR(khmtt16, 2, 2);
+
+static inline void do_kdmbb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i)] == INT16_MIN) {
+ d[H4(i / 2)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i / 2)] = (int64_t)a[H2(i)] * b[H2(i)] << 1;
+ }
+}
+
+RVPR(kdmbb16, 2, 2);
+
+static inline void do_kdmbt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ d[H4(i / 2)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i / 2)] = (int64_t)a[H2(i)] * b[H2(i + 1)] << 1;
+ }
+}
+
+RVPR(kdmbt16, 2, 2);
+
+static inline void do_kdmtt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i + 1)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ d[H4(i / 2)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i / 2)] = (int64_t)a[H2(i + 1)] * b[H2(i + 1)] << 1;
+ }
+}
+
+RVPR(kdmtt16, 2, 2);
+
+static inline void do_kdmabb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i)] * b[H2(i)] << 1;
+ }
+ d[H4(i / 2)] = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmabb16, 2, 2);
+
+static inline void do_kdmabt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i)] * b[H2(i + 1)] << 1;
+ }
+ d[H4(i / 2)] = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmabt16, 2, 2);
+
+static inline void do_kdmatt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i + 1)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i + 1)] * b[H2(i + 1)] << 1;
+ }
+ *d = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmatt16, 2, 2);
+
+
#endif
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org,
alistair23@gmail.com, palmer@dabbelt.com,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
Date: Fri, 12 Feb 2021 23:02:50 +0800 [thread overview]
Message-ID: <20210212150256.885-33-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 10 ++
target/riscv/insn32-64.decode | 10 ++
target/riscv/insn_trans/trans_rvp.c.inc | 11 ++
target/riscv/packed_helper.c | 141 ++++++++++++++++++++++++
4 files changed, 172 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 384b42ce90..f8521a5388 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1440,4 +1440,14 @@ DEF_HELPER_3(umin32, tl, env, tl, tl)
DEF_HELPER_3(smax32, tl, env, tl, tl)
DEF_HELPER_3(umax32, tl, env, tl, tl)
DEF_HELPER_2(kabs32, tl, env, tl)
+
+DEF_HELPER_3(khmbb16, tl, env, tl, tl)
+DEF_HELPER_3(khmbt16, tl, env, tl, tl)
+DEF_HELPER_3(khmtt16, tl, env, tl, tl)
+DEF_HELPER_3(kdmbb16, tl, env, tl, tl)
+DEF_HELPER_3(kdmbt16, tl, env, tl, tl)
+DEF_HELPER_3(kdmtt16, tl, env, tl, tl)
+DEF_HELPER_4(kdmabb16, tl, env, tl, tl, tl)
+DEF_HELPER_4(kdmabt16, tl, env, tl, tl, tl)
+DEF_HELPER_4(kdmatt16, tl, env, tl, tl, tl)
#endif
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index a2b8831467..2e1c1817e4 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -135,3 +135,13 @@ umin32 1010000 ..... ..... 010 ..... 1111111 @r
smax32 1001001 ..... ..... 010 ..... 1111111 @r
umax32 1010001 ..... ..... 010 ..... 1111111 @r
kabs32 1010110 10010 ..... 000 ..... 1111111 @r2
+
+khmbb16 1101110 ..... ..... 001 ..... 1111111 @r
+khmbt16 1110110 ..... ..... 001 ..... 1111111 @r
+khmtt16 1111110 ..... ..... 001 ..... 1111111 @r
+kdmbb16 1101101 ..... ..... 001 ..... 1111111 @r
+kdmbt16 1110101 ..... ..... 001 ..... 1111111 @r
+kdmtt16 1111101 ..... ..... 001 ..... 1111111 @r
+kdmabb16 1101100 ..... ..... 001 ..... 1111111 @r
+kdmabt16 1110100 ..... ..... 001 ..... 1111111 @r
+kdmatt16 1111100 ..... ..... 001 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index ce144ee5c0..2b4418abd8 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1179,4 +1179,15 @@ GEN_RVP_R_OOL(umin32);
GEN_RVP_R_OOL(smax32);
GEN_RVP_R_OOL(umax32);
GEN_RVP_R2_OOL(kabs32);
+
+/* (RV64 Only) SIMD Q15 saturating Multiply Instructions */
+GEN_RVP_R_OOL(khmbb16);
+GEN_RVP_R_OOL(khmbt16);
+GEN_RVP_R_OOL(khmtt16);
+GEN_RVP_R_OOL(kdmbb16);
+GEN_RVP_R_OOL(kdmbt16);
+GEN_RVP_R_OOL(kdmtt16);
+GEN_RVP_R_ACC_OOL(kdmabb16);
+GEN_RVP_R_ACC_OOL(kdmabt16);
+GEN_RVP_R_ACC_OOL(kdmatt16);
#endif
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index c8a92f5b7d..5636848aaf 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3432,4 +3432,145 @@ static inline void do_kabs32(CPURISCVState *env, void *vd, void *va, uint8_t i)
}
RVPR2(kabs32, 1, 4);
+
+/* (RV64 Only) SIMD Q15 saturating Multiply Instructions */
+static inline void do_khmbb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ d[H4(i / 2)] = sat64(env, (int64_t)a[H2(i)] * b[H2(i)] >> 15, 15);
+}
+
+RVPR(khmbb16, 2, 2);
+
+static inline void do_khmbt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ d[H4(i / 2)] = sat64(env, (int64_t)a[H2(i)] * b[H2(i + 1)] >> 15, 15);
+}
+
+RVPR(khmbt16, 2, 2);
+
+static inline void do_khmtt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ d[H4(i / 2)] = sat64(env, (int64_t)a[H2(i + 1)] * b[H2(i + 1)] >> 15, 15);
+}
+
+RVPR(khmtt16, 2, 2);
+
+static inline void do_kdmbb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i)] == INT16_MIN) {
+ d[H4(i / 2)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i / 2)] = (int64_t)a[H2(i)] * b[H2(i)] << 1;
+ }
+}
+
+RVPR(kdmbb16, 2, 2);
+
+static inline void do_kdmbt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ d[H4(i / 2)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i / 2)] = (int64_t)a[H2(i)] * b[H2(i + 1)] << 1;
+ }
+}
+
+RVPR(kdmbt16, 2, 2);
+
+static inline void do_kdmtt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+
+ if (a[H2(i + 1)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ d[H4(i / 2)] = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ d[H4(i / 2)] = (int64_t)a[H2(i + 1)] * b[H2(i + 1)] << 1;
+ }
+}
+
+RVPR(kdmtt16, 2, 2);
+
+static inline void do_kdmabb16(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i)] * b[H2(i)] << 1;
+ }
+ d[H4(i / 2)] = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmabb16, 2, 2);
+
+static inline void do_kdmabt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i)] * b[H2(i + 1)] << 1;
+ }
+ d[H4(i / 2)] = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmabt16, 2, 2);
+
+static inline void do_kdmatt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+
+{
+ int32_t *d = vd;
+ int16_t *a = va, *b = vb;
+ int32_t *c = vc, m0;
+
+ if (a[H2(i + 1)] == INT16_MIN && b[H2(i + 1)] == INT16_MIN) {
+ m0 = INT32_MAX;
+ env->vxsat = 0x1;
+ } else {
+ m0 = (int32_t)a[H2(i + 1)] * b[H2(i + 1)] << 1;
+ }
+ *d = sadd32(env, 0, c[H4(i)], m0);
+}
+
+RVPR_ACC(kdmatt16, 2, 2);
+
+
#endif
--
2.17.1
next prev parent reply other threads:[~2021-02-12 16:11 UTC|newest]
Thread overview: 150+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-09 14:08 ` Alistair Francis
2021-03-09 14:08 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-09 14:10 ` Alistair Francis
2021-03-09 14:10 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 18:52 ` Richard Henderson
2021-02-12 18:52 ` Richard Henderson
2021-03-09 14:11 ` Alistair Francis
2021-03-09 14:11 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 18:03 ` Richard Henderson
2021-02-12 18:03 ` Richard Henderson
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 16:20 ` Richard Henderson
2021-02-18 16:20 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 16:21 ` Richard Henderson
2021-02-18 16:21 ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:22 ` Alistair Francis
2021-03-15 21:22 ` Alistair Francis
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 6:15 ` Palmer Dabbelt
2021-05-26 6:15 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:25 ` Alistair Francis
2021-03-15 21:25 ` Alistair Francis
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 19:54 ` Alistair Francis
2021-03-16 19:54 ` Alistair Francis
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 20:39 ` Alistair Francis
2021-03-17 20:39 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:27 ` Alistair Francis
2021-03-15 21:27 ` Alistair Francis
2021-05-24 4:46 ` Palmer Dabbelt
2021-05-24 4:46 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:28 ` Alistair Francis
2021-03-15 21:28 ` Alistair Francis
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:31 ` Alistair Francis
2021-03-15 21:31 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:33 ` Alistair Francis
2021-03-15 21:33 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-15 21:35 ` Alistair Francis
2021-03-15 21:35 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-16 14:38 ` Alistair Francis
2021-03-16 14:38 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-16 14:40 ` Alistair Francis
2021-03-16 14:40 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-16 14:42 ` Alistair Francis
2021-03-16 14:42 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-16 16:01 ` Alistair Francis
2021-03-16 16:01 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-16 19:44 ` Alistair Francis
2021-03-16 19:44 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei [this message]
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei
2021-03-05 6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-03-05 6:14 ` LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-15 4:46 ` Alistair Francis
2021-04-15 4:46 ` Alistair Francis
2021-04-15 5:50 ` LIU Zhiwei
2021-04-15 5:50 ` LIU Zhiwei
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