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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Tom Joseph <tjoseph@cadence.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: [PATCH v3 3/4] dt-bindings: PCI: ti,j721e: Add endpoint mode dt-bindings for TI's AM64 SoC
Date: Mon, 22 Feb 2021 17:10:29 +0530	[thread overview]
Message-ID: <20210222114030.26445-4-kishon@ti.com> (raw)
In-Reply-To: <20210222114030.26445-1-kishon@ti.com>

Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP
used in J7200, however AM64 is a non-coherent architecture.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml         | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index d06f0c4464c6..aed437dac363 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -16,12 +16,14 @@ allOf:
 properties:
   compatible:
     oneOf:
-      - description: PCIe EP controller in J7200
+      - const: ti,j721e-pcie-ep
+      - description: PCIe EP controller in AM64
         items:
-          - const: ti,j7200-pcie-ep
+          - const: ti,am64-pcie-ep
           - const: ti,j721e-pcie-ep
-      - description: PCIe EP controller in J721E
+      - description: PCIe EP controller in J7200
         items:
+          - const: ti,j7200-pcie-ep
           - const: ti,j721e-pcie-ep
 
   reg:
@@ -66,7 +68,6 @@ required:
   - power-domains
   - clocks
   - clock-names
-  - dma-coherent
   - max-functions
   - phys
   - phy-names
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh+dt@kernel.org>,
	Tom Joseph <tjoseph@cadence.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: [PATCH v3 3/4] dt-bindings: PCI: ti, j721e: Add endpoint mode dt-bindings for TI's AM64 SoC
Date: Mon, 22 Feb 2021 17:10:29 +0530	[thread overview]
Message-ID: <20210222114030.26445-4-kishon@ti.com> (raw)
In-Reply-To: <20210222114030.26445-1-kishon@ti.com>

Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP
used in J7200, however AM64 is a non-coherent architecture.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml         | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
index d06f0c4464c6..aed437dac363 100644
--- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
@@ -16,12 +16,14 @@ allOf:
 properties:
   compatible:
     oneOf:
-      - description: PCIe EP controller in J7200
+      - const: ti,j721e-pcie-ep
+      - description: PCIe EP controller in AM64
         items:
-          - const: ti,j7200-pcie-ep
+          - const: ti,am64-pcie-ep
           - const: ti,j721e-pcie-ep
-      - description: PCIe EP controller in J721E
+      - description: PCIe EP controller in J7200
         items:
+          - const: ti,j7200-pcie-ep
           - const: ti,j721e-pcie-ep
 
   reg:
@@ -66,7 +68,6 @@ required:
   - power-domains
   - clocks
   - clock-names
-  - dma-coherent
   - max-functions
   - phys
   - phy-names
-- 
2.17.1


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  parent reply	other threads:[~2021-02-22 11:41 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-22 11:40 [PATCH v3 0/4] AM64: Add PCIe bindings and driver support Kishon Vijay Abraham I
2021-02-22 11:40 ` Kishon Vijay Abraham I
2021-02-22 11:40 ` [PATCH v3 1/4] dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the connector Kishon Vijay Abraham I
2021-02-22 11:40   ` [PATCH v3 1/4] dt-bindings: PCI: ti, j721e: " Kishon Vijay Abraham I
2021-02-22 17:29   ` [PATCH v3 1/4] dt-bindings: PCI: ti,j721e: " Krzysztof Wilczyński
2021-02-22 17:29     ` Krzysztof Wilczyński
2021-02-22 11:40 ` [PATCH v3 2/4] dt-bindings: PCI: ti,j721e: Add host mode dt-bindings for TI's AM64 SoC Kishon Vijay Abraham I
2021-02-22 11:40   ` [PATCH v3 2/4] dt-bindings: PCI: ti, j721e: " Kishon Vijay Abraham I
2021-03-05 23:28   ` Rob Herring
2021-03-05 23:28     ` Rob Herring
2021-02-22 11:40 ` Kishon Vijay Abraham I [this message]
2021-02-22 11:40   ` [PATCH v3 3/4] dt-bindings: PCI: ti, j721e: Add endpoint " Kishon Vijay Abraham I
2021-03-05 23:29   ` Rob Herring
2021-03-05 23:29     ` Rob Herring
2021-02-22 11:40 ` [PATCH v3 4/4] PCI: j721e: Add support to provide refclk to PCIe connector Kishon Vijay Abraham I
2021-02-22 11:40   ` Kishon Vijay Abraham I
2021-02-23  7:50   ` Dan Carpenter
2021-02-23  7:50     ` Dan Carpenter
2021-02-23  7:50     ` Dan Carpenter
2021-02-23  7:50     ` Dan Carpenter

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