From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
To: p.zabel@pengutronix.de, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com,
ezequiel@collabora.com, mchehab@kernel.org,
gregkh@linuxfoundation.org
Cc: kernel@pengutronix.de, linux-imx@nxp.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-media@vger.kernel.org,
linux-rockchip@lists.infradead.org, devel@driverdev.osuosl.org,
kernel@collabora.com, benjamin.gaignard@collabora.com
Subject: [PATCH v2 3/5] reset: Add reset driver for IMX8MQ VPU block
Date: Fri, 26 Feb 2021 10:11:26 +0100 [thread overview]
Message-ID: <20210226091128.14379-4-benjamin.gaignard@collabora.com> (raw)
In-Reply-To: <20210226091128.14379-1-benjamin.gaignard@collabora.com>
IMX8MQ SoC got a dedicated hardware block to reset the video processor
units (G1 and G2).
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-imx8mq-vpu.c | 169 +++++++++++++++++++++++++++++++
3 files changed, 178 insertions(+)
create mode 100644 drivers/reset/reset-imx8mq-vpu.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..fa95380b271a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -80,6 +80,14 @@ config RESET_IMX7
help
This enables the reset controller driver for i.MX7 SoCs.
+config RESET_VPU_IMX8MQ
+ tristate "i.MX8MQ VPU Reset Driver"
+ depends on HAS_IOMEM
+ depends on (ARM64 && ARCH_MXC) || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ This enables the VPU reset controller driver for i.MX8MQ SoCs.
+
config RESET_INTEL_GW
bool "Intel Reset Controller Driver"
depends on OF && HAS_IOMEM
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..6007e0cdfc05 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_VPU_IMX8MQ) += reset-imx8mq-vpu.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
diff --git a/drivers/reset/reset-imx8mq-vpu.c b/drivers/reset/reset-imx8mq-vpu.c
new file mode 100644
index 000000000000..14c589f19266
--- /dev/null
+++ b/drivers/reset/reset-imx8mq-vpu.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, Collabora
+ *
+ * i.MX8MQ VPU Reset Controller driver
+ *
+ * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <dt-bindings/reset/imx8mq-vpu-reset.h>
+
+#define CTRL_SOFT_RESET 0x00
+#define RESET_G1 ((u32)BIT(1))
+#define RESET_G2 ((u32)BIT(0))
+
+#define CTRL_ENABLE 0x04
+#define ENABLE_G1 BIT(1)
+#define ENABLE_G2 BIT(0)
+
+#define CTRL_G1_DEC_FUSE 0x08
+#define CTRL_G1_PP_FUSE 0x0c
+#define CTRL_G2_DEC_FUSE 0x10
+
+struct imx8mq_vpu_reset {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ struct clk_bulk_data *clocks;
+ int num_clocks;
+ struct device *dev;
+};
+
+static inline struct imx8mq_vpu_reset *to_imx8mq_vpu_reset(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct imx8mq_vpu_reset, rcdev);
+}
+
+static int imx8mq_vpu_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct imx8mq_vpu_reset *reset = to_imx8mq_vpu_reset(rcdev);
+ int ret = -EINVAL;
+
+ ret = clk_bulk_prepare_enable(reset->num_clocks, reset->clocks);
+ if (ret) {
+ dev_err(reset->dev, "Failed to prepare clocks\n");
+ return ret;
+ }
+
+ switch (id) {
+ case IMX8MQ_RESET_VPU_RESET_G1:
+ ret = regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G1, ~RESET_G1);
+ ret |= regmap_update_bits(reset->regmap, CTRL_ENABLE, ENABLE_G1, ENABLE_G1);
+ break;
+ case IMX8MQ_RESET_VPU_RESET_G2:
+ ret = regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G2, ~RESET_G2);
+ ret |= regmap_update_bits(reset->regmap, CTRL_ENABLE, ENABLE_G2, ENABLE_G2);
+ break;
+ }
+
+ /* Set values of the fuse registers */
+ ret |= regmap_write(reset->regmap, CTRL_G1_DEC_FUSE, 0xffffffff);
+ ret |= regmap_write(reset->regmap, CTRL_G1_PP_FUSE, 0xffffffff);
+ ret |= regmap_write(reset->regmap, CTRL_G2_DEC_FUSE, 0xffffffff);
+
+ clk_bulk_disable_unprepare(reset->num_clocks, reset->clocks);
+
+ return ret;
+}
+
+static int imx8mq_vpu_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct imx8mq_vpu_reset *reset = to_imx8mq_vpu_reset(rcdev);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(reset->num_clocks, reset->clocks);
+ if (ret) {
+ dev_err(reset->dev, "Failed to prepare clocks\n");
+ return ret;
+ }
+
+ switch (id) {
+ case IMX8MQ_RESET_VPU_RESET_G1:
+ return regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G1, RESET_G1);
+ case IMX8MQ_RESET_VPU_RESET_G2:
+ return regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G2, RESET_G2);
+ }
+
+ clk_bulk_disable_unprepare(reset->num_clocks, reset->clocks);
+
+ return -EINVAL;
+}
+
+static int imx8mq_vpu_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = imx8mq_vpu_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ udelay(2);
+
+ return imx8mq_vpu_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops imx8mq_vpu_reset_ops = {
+ .reset = imx8mq_vpu_reset_dev,
+ .assert = imx8mq_vpu_reset_assert,
+ .deassert = imx8mq_vpu_reset_deassert,
+};
+
+static int imx8mq_vpu_reset_probe(struct platform_device *pdev)
+{
+ struct imx8mq_vpu_reset *reset;
+ struct device *dev = &pdev->dev;
+ struct regmap_config config = { .name = "vpu-reset" };
+
+ reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL);
+ if (!reset)
+ return -ENOMEM;
+
+ reset->regmap = device_node_to_regmap(dev->of_node);
+ if (IS_ERR(reset->regmap)) {
+ dev_err(dev, "Unable to get imx8mq-vpu-reset regmap");
+ return PTR_ERR(reset->regmap);
+ }
+ regmap_attach_dev(dev, reset->regmap, &config);
+
+ reset->num_clocks = devm_clk_bulk_get_all(dev, &reset->clocks);
+ if (!reset->num_clocks)
+ return -EINVAL;
+
+ reset->rcdev.owner = THIS_MODULE;
+ reset->rcdev.nr_resets = 2;
+ reset->rcdev.ops = &imx8mq_vpu_reset_ops;
+ reset->rcdev.of_node = dev->of_node;
+ reset->dev = dev;
+
+ return devm_reset_controller_register(dev, &reset->rcdev);
+}
+
+static const struct of_device_id imx8mq_vpu_reset_dt_ids[] = {
+ { .compatible = "fsl,imx8mq-vpu-reset",},
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx8mq_vpu_reset_dt_ids);
+
+static struct platform_driver imx8mq_vpu_reset_driver = {
+ .probe = imx8mq_vpu_reset_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = imx8mq_vpu_reset_dt_ids,
+ },
+};
+module_platform_driver(imx8mq_vpu_reset_driver);
+
+MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@collabora.com>");
+MODULE_DESCRIPTION("NXP i.MX8MQ VPU reset driver");
+MODULE_LICENSE("GPL v2");
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
To: p.zabel@pengutronix.de, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com,
ezequiel@collabora.com, mchehab@kernel.org,
gregkh@linuxfoundation.org
Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org,
benjamin.gaignard@collabora.com, linux-kernel@vger.kernel.org,
linux-rockchip@lists.infradead.org, linux-imx@nxp.com,
kernel@pengutronix.de, kernel@collabora.com,
linux-arm-kernel@lists.infradead.org,
linux-media@vger.kernel.org
Subject: [PATCH v2 3/5] reset: Add reset driver for IMX8MQ VPU block
Date: Fri, 26 Feb 2021 10:11:26 +0100 [thread overview]
Message-ID: <20210226091128.14379-4-benjamin.gaignard@collabora.com> (raw)
In-Reply-To: <20210226091128.14379-1-benjamin.gaignard@collabora.com>
IMX8MQ SoC got a dedicated hardware block to reset the video processor
units (G1 and G2).
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-imx8mq-vpu.c | 169 +++++++++++++++++++++++++++++++
3 files changed, 178 insertions(+)
create mode 100644 drivers/reset/reset-imx8mq-vpu.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..fa95380b271a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -80,6 +80,14 @@ config RESET_IMX7
help
This enables the reset controller driver for i.MX7 SoCs.
+config RESET_VPU_IMX8MQ
+ tristate "i.MX8MQ VPU Reset Driver"
+ depends on HAS_IOMEM
+ depends on (ARM64 && ARCH_MXC) || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ This enables the VPU reset controller driver for i.MX8MQ SoCs.
+
config RESET_INTEL_GW
bool "Intel Reset Controller Driver"
depends on OF && HAS_IOMEM
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..6007e0cdfc05 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_VPU_IMX8MQ) += reset-imx8mq-vpu.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
diff --git a/drivers/reset/reset-imx8mq-vpu.c b/drivers/reset/reset-imx8mq-vpu.c
new file mode 100644
index 000000000000..14c589f19266
--- /dev/null
+++ b/drivers/reset/reset-imx8mq-vpu.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, Collabora
+ *
+ * i.MX8MQ VPU Reset Controller driver
+ *
+ * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <dt-bindings/reset/imx8mq-vpu-reset.h>
+
+#define CTRL_SOFT_RESET 0x00
+#define RESET_G1 ((u32)BIT(1))
+#define RESET_G2 ((u32)BIT(0))
+
+#define CTRL_ENABLE 0x04
+#define ENABLE_G1 BIT(1)
+#define ENABLE_G2 BIT(0)
+
+#define CTRL_G1_DEC_FUSE 0x08
+#define CTRL_G1_PP_FUSE 0x0c
+#define CTRL_G2_DEC_FUSE 0x10
+
+struct imx8mq_vpu_reset {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ struct clk_bulk_data *clocks;
+ int num_clocks;
+ struct device *dev;
+};
+
+static inline struct imx8mq_vpu_reset *to_imx8mq_vpu_reset(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct imx8mq_vpu_reset, rcdev);
+}
+
+static int imx8mq_vpu_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct imx8mq_vpu_reset *reset = to_imx8mq_vpu_reset(rcdev);
+ int ret = -EINVAL;
+
+ ret = clk_bulk_prepare_enable(reset->num_clocks, reset->clocks);
+ if (ret) {
+ dev_err(reset->dev, "Failed to prepare clocks\n");
+ return ret;
+ }
+
+ switch (id) {
+ case IMX8MQ_RESET_VPU_RESET_G1:
+ ret = regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G1, ~RESET_G1);
+ ret |= regmap_update_bits(reset->regmap, CTRL_ENABLE, ENABLE_G1, ENABLE_G1);
+ break;
+ case IMX8MQ_RESET_VPU_RESET_G2:
+ ret = regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G2, ~RESET_G2);
+ ret |= regmap_update_bits(reset->regmap, CTRL_ENABLE, ENABLE_G2, ENABLE_G2);
+ break;
+ }
+
+ /* Set values of the fuse registers */
+ ret |= regmap_write(reset->regmap, CTRL_G1_DEC_FUSE, 0xffffffff);
+ ret |= regmap_write(reset->regmap, CTRL_G1_PP_FUSE, 0xffffffff);
+ ret |= regmap_write(reset->regmap, CTRL_G2_DEC_FUSE, 0xffffffff);
+
+ clk_bulk_disable_unprepare(reset->num_clocks, reset->clocks);
+
+ return ret;
+}
+
+static int imx8mq_vpu_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct imx8mq_vpu_reset *reset = to_imx8mq_vpu_reset(rcdev);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(reset->num_clocks, reset->clocks);
+ if (ret) {
+ dev_err(reset->dev, "Failed to prepare clocks\n");
+ return ret;
+ }
+
+ switch (id) {
+ case IMX8MQ_RESET_VPU_RESET_G1:
+ return regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G1, RESET_G1);
+ case IMX8MQ_RESET_VPU_RESET_G2:
+ return regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G2, RESET_G2);
+ }
+
+ clk_bulk_disable_unprepare(reset->num_clocks, reset->clocks);
+
+ return -EINVAL;
+}
+
+static int imx8mq_vpu_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = imx8mq_vpu_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ udelay(2);
+
+ return imx8mq_vpu_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops imx8mq_vpu_reset_ops = {
+ .reset = imx8mq_vpu_reset_dev,
+ .assert = imx8mq_vpu_reset_assert,
+ .deassert = imx8mq_vpu_reset_deassert,
+};
+
+static int imx8mq_vpu_reset_probe(struct platform_device *pdev)
+{
+ struct imx8mq_vpu_reset *reset;
+ struct device *dev = &pdev->dev;
+ struct regmap_config config = { .name = "vpu-reset" };
+
+ reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL);
+ if (!reset)
+ return -ENOMEM;
+
+ reset->regmap = device_node_to_regmap(dev->of_node);
+ if (IS_ERR(reset->regmap)) {
+ dev_err(dev, "Unable to get imx8mq-vpu-reset regmap");
+ return PTR_ERR(reset->regmap);
+ }
+ regmap_attach_dev(dev, reset->regmap, &config);
+
+ reset->num_clocks = devm_clk_bulk_get_all(dev, &reset->clocks);
+ if (!reset->num_clocks)
+ return -EINVAL;
+
+ reset->rcdev.owner = THIS_MODULE;
+ reset->rcdev.nr_resets = 2;
+ reset->rcdev.ops = &imx8mq_vpu_reset_ops;
+ reset->rcdev.of_node = dev->of_node;
+ reset->dev = dev;
+
+ return devm_reset_controller_register(dev, &reset->rcdev);
+}
+
+static const struct of_device_id imx8mq_vpu_reset_dt_ids[] = {
+ { .compatible = "fsl,imx8mq-vpu-reset",},
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx8mq_vpu_reset_dt_ids);
+
+static struct platform_driver imx8mq_vpu_reset_driver = {
+ .probe = imx8mq_vpu_reset_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = imx8mq_vpu_reset_dt_ids,
+ },
+};
+module_platform_driver(imx8mq_vpu_reset_driver);
+
+MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@collabora.com>");
+MODULE_DESCRIPTION("NXP i.MX8MQ VPU reset driver");
+MODULE_LICENSE("GPL v2");
--
2.25.1
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
WARNING: multiple messages have this Message-ID (diff)
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
To: p.zabel@pengutronix.de, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com,
ezequiel@collabora.com, mchehab@kernel.org,
gregkh@linuxfoundation.org
Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org,
benjamin.gaignard@collabora.com, linux-kernel@vger.kernel.org,
linux-rockchip@lists.infradead.org, linux-imx@nxp.com,
kernel@pengutronix.de, kernel@collabora.com,
linux-arm-kernel@lists.infradead.org,
linux-media@vger.kernel.org
Subject: [PATCH v2 3/5] reset: Add reset driver for IMX8MQ VPU block
Date: Fri, 26 Feb 2021 10:11:26 +0100 [thread overview]
Message-ID: <20210226091128.14379-4-benjamin.gaignard@collabora.com> (raw)
In-Reply-To: <20210226091128.14379-1-benjamin.gaignard@collabora.com>
IMX8MQ SoC got a dedicated hardware block to reset the video processor
units (G1 and G2).
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-imx8mq-vpu.c | 169 +++++++++++++++++++++++++++++++
3 files changed, 178 insertions(+)
create mode 100644 drivers/reset/reset-imx8mq-vpu.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..fa95380b271a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -80,6 +80,14 @@ config RESET_IMX7
help
This enables the reset controller driver for i.MX7 SoCs.
+config RESET_VPU_IMX8MQ
+ tristate "i.MX8MQ VPU Reset Driver"
+ depends on HAS_IOMEM
+ depends on (ARM64 && ARCH_MXC) || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ This enables the VPU reset controller driver for i.MX8MQ SoCs.
+
config RESET_INTEL_GW
bool "Intel Reset Controller Driver"
depends on OF && HAS_IOMEM
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..6007e0cdfc05 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_VPU_IMX8MQ) += reset-imx8mq-vpu.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
diff --git a/drivers/reset/reset-imx8mq-vpu.c b/drivers/reset/reset-imx8mq-vpu.c
new file mode 100644
index 000000000000..14c589f19266
--- /dev/null
+++ b/drivers/reset/reset-imx8mq-vpu.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, Collabora
+ *
+ * i.MX8MQ VPU Reset Controller driver
+ *
+ * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <dt-bindings/reset/imx8mq-vpu-reset.h>
+
+#define CTRL_SOFT_RESET 0x00
+#define RESET_G1 ((u32)BIT(1))
+#define RESET_G2 ((u32)BIT(0))
+
+#define CTRL_ENABLE 0x04
+#define ENABLE_G1 BIT(1)
+#define ENABLE_G2 BIT(0)
+
+#define CTRL_G1_DEC_FUSE 0x08
+#define CTRL_G1_PP_FUSE 0x0c
+#define CTRL_G2_DEC_FUSE 0x10
+
+struct imx8mq_vpu_reset {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ struct clk_bulk_data *clocks;
+ int num_clocks;
+ struct device *dev;
+};
+
+static inline struct imx8mq_vpu_reset *to_imx8mq_vpu_reset(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct imx8mq_vpu_reset, rcdev);
+}
+
+static int imx8mq_vpu_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct imx8mq_vpu_reset *reset = to_imx8mq_vpu_reset(rcdev);
+ int ret = -EINVAL;
+
+ ret = clk_bulk_prepare_enable(reset->num_clocks, reset->clocks);
+ if (ret) {
+ dev_err(reset->dev, "Failed to prepare clocks\n");
+ return ret;
+ }
+
+ switch (id) {
+ case IMX8MQ_RESET_VPU_RESET_G1:
+ ret = regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G1, ~RESET_G1);
+ ret |= regmap_update_bits(reset->regmap, CTRL_ENABLE, ENABLE_G1, ENABLE_G1);
+ break;
+ case IMX8MQ_RESET_VPU_RESET_G2:
+ ret = regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G2, ~RESET_G2);
+ ret |= regmap_update_bits(reset->regmap, CTRL_ENABLE, ENABLE_G2, ENABLE_G2);
+ break;
+ }
+
+ /* Set values of the fuse registers */
+ ret |= regmap_write(reset->regmap, CTRL_G1_DEC_FUSE, 0xffffffff);
+ ret |= regmap_write(reset->regmap, CTRL_G1_PP_FUSE, 0xffffffff);
+ ret |= regmap_write(reset->regmap, CTRL_G2_DEC_FUSE, 0xffffffff);
+
+ clk_bulk_disable_unprepare(reset->num_clocks, reset->clocks);
+
+ return ret;
+}
+
+static int imx8mq_vpu_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct imx8mq_vpu_reset *reset = to_imx8mq_vpu_reset(rcdev);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(reset->num_clocks, reset->clocks);
+ if (ret) {
+ dev_err(reset->dev, "Failed to prepare clocks\n");
+ return ret;
+ }
+
+ switch (id) {
+ case IMX8MQ_RESET_VPU_RESET_G1:
+ return regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G1, RESET_G1);
+ case IMX8MQ_RESET_VPU_RESET_G2:
+ return regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G2, RESET_G2);
+ }
+
+ clk_bulk_disable_unprepare(reset->num_clocks, reset->clocks);
+
+ return -EINVAL;
+}
+
+static int imx8mq_vpu_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = imx8mq_vpu_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ udelay(2);
+
+ return imx8mq_vpu_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops imx8mq_vpu_reset_ops = {
+ .reset = imx8mq_vpu_reset_dev,
+ .assert = imx8mq_vpu_reset_assert,
+ .deassert = imx8mq_vpu_reset_deassert,
+};
+
+static int imx8mq_vpu_reset_probe(struct platform_device *pdev)
+{
+ struct imx8mq_vpu_reset *reset;
+ struct device *dev = &pdev->dev;
+ struct regmap_config config = { .name = "vpu-reset" };
+
+ reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL);
+ if (!reset)
+ return -ENOMEM;
+
+ reset->regmap = device_node_to_regmap(dev->of_node);
+ if (IS_ERR(reset->regmap)) {
+ dev_err(dev, "Unable to get imx8mq-vpu-reset regmap");
+ return PTR_ERR(reset->regmap);
+ }
+ regmap_attach_dev(dev, reset->regmap, &config);
+
+ reset->num_clocks = devm_clk_bulk_get_all(dev, &reset->clocks);
+ if (!reset->num_clocks)
+ return -EINVAL;
+
+ reset->rcdev.owner = THIS_MODULE;
+ reset->rcdev.nr_resets = 2;
+ reset->rcdev.ops = &imx8mq_vpu_reset_ops;
+ reset->rcdev.of_node = dev->of_node;
+ reset->dev = dev;
+
+ return devm_reset_controller_register(dev, &reset->rcdev);
+}
+
+static const struct of_device_id imx8mq_vpu_reset_dt_ids[] = {
+ { .compatible = "fsl,imx8mq-vpu-reset",},
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx8mq_vpu_reset_dt_ids);
+
+static struct platform_driver imx8mq_vpu_reset_driver = {
+ .probe = imx8mq_vpu_reset_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = imx8mq_vpu_reset_dt_ids,
+ },
+};
+module_platform_driver(imx8mq_vpu_reset_driver);
+
+MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@collabora.com>");
+MODULE_DESCRIPTION("NXP i.MX8MQ VPU reset driver");
+MODULE_LICENSE("GPL v2");
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID (diff)
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
To: p.zabel@pengutronix.de, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com,
ezequiel@collabora.com, mchehab@kernel.org,
gregkh@linuxfoundation.org
Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org,
benjamin.gaignard@collabora.com, linux-kernel@vger.kernel.org,
linux-rockchip@lists.infradead.org, linux-imx@nxp.com,
kernel@pengutronix.de, kernel@collabora.com,
linux-arm-kernel@lists.infradead.org,
linux-media@vger.kernel.org
Subject: [PATCH v2 3/5] reset: Add reset driver for IMX8MQ VPU block
Date: Fri, 26 Feb 2021 10:11:26 +0100 [thread overview]
Message-ID: <20210226091128.14379-4-benjamin.gaignard@collabora.com> (raw)
In-Reply-To: <20210226091128.14379-1-benjamin.gaignard@collabora.com>
IMX8MQ SoC got a dedicated hardware block to reset the video processor
units (G1 and G2).
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-imx8mq-vpu.c | 169 +++++++++++++++++++++++++++++++
3 files changed, 178 insertions(+)
create mode 100644 drivers/reset/reset-imx8mq-vpu.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..fa95380b271a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -80,6 +80,14 @@ config RESET_IMX7
help
This enables the reset controller driver for i.MX7 SoCs.
+config RESET_VPU_IMX8MQ
+ tristate "i.MX8MQ VPU Reset Driver"
+ depends on HAS_IOMEM
+ depends on (ARM64 && ARCH_MXC) || COMPILE_TEST
+ select MFD_SYSCON
+ help
+ This enables the VPU reset controller driver for i.MX8MQ SoCs.
+
config RESET_INTEL_GW
bool "Intel Reset Controller Driver"
depends on OF && HAS_IOMEM
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..6007e0cdfc05 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_VPU_IMX8MQ) += reset-imx8mq-vpu.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
diff --git a/drivers/reset/reset-imx8mq-vpu.c b/drivers/reset/reset-imx8mq-vpu.c
new file mode 100644
index 000000000000..14c589f19266
--- /dev/null
+++ b/drivers/reset/reset-imx8mq-vpu.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, Collabora
+ *
+ * i.MX8MQ VPU Reset Controller driver
+ *
+ * Author: Benjamin Gaignard <benjamin.gaignard@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/regmap.h>
+#include <dt-bindings/reset/imx8mq-vpu-reset.h>
+
+#define CTRL_SOFT_RESET 0x00
+#define RESET_G1 ((u32)BIT(1))
+#define RESET_G2 ((u32)BIT(0))
+
+#define CTRL_ENABLE 0x04
+#define ENABLE_G1 BIT(1)
+#define ENABLE_G2 BIT(0)
+
+#define CTRL_G1_DEC_FUSE 0x08
+#define CTRL_G1_PP_FUSE 0x0c
+#define CTRL_G2_DEC_FUSE 0x10
+
+struct imx8mq_vpu_reset {
+ struct reset_controller_dev rcdev;
+ struct regmap *regmap;
+ struct clk_bulk_data *clocks;
+ int num_clocks;
+ struct device *dev;
+};
+
+static inline struct imx8mq_vpu_reset *to_imx8mq_vpu_reset(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct imx8mq_vpu_reset, rcdev);
+}
+
+static int imx8mq_vpu_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct imx8mq_vpu_reset *reset = to_imx8mq_vpu_reset(rcdev);
+ int ret = -EINVAL;
+
+ ret = clk_bulk_prepare_enable(reset->num_clocks, reset->clocks);
+ if (ret) {
+ dev_err(reset->dev, "Failed to prepare clocks\n");
+ return ret;
+ }
+
+ switch (id) {
+ case IMX8MQ_RESET_VPU_RESET_G1:
+ ret = regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G1, ~RESET_G1);
+ ret |= regmap_update_bits(reset->regmap, CTRL_ENABLE, ENABLE_G1, ENABLE_G1);
+ break;
+ case IMX8MQ_RESET_VPU_RESET_G2:
+ ret = regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G2, ~RESET_G2);
+ ret |= regmap_update_bits(reset->regmap, CTRL_ENABLE, ENABLE_G2, ENABLE_G2);
+ break;
+ }
+
+ /* Set values of the fuse registers */
+ ret |= regmap_write(reset->regmap, CTRL_G1_DEC_FUSE, 0xffffffff);
+ ret |= regmap_write(reset->regmap, CTRL_G1_PP_FUSE, 0xffffffff);
+ ret |= regmap_write(reset->regmap, CTRL_G2_DEC_FUSE, 0xffffffff);
+
+ clk_bulk_disable_unprepare(reset->num_clocks, reset->clocks);
+
+ return ret;
+}
+
+static int imx8mq_vpu_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct imx8mq_vpu_reset *reset = to_imx8mq_vpu_reset(rcdev);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(reset->num_clocks, reset->clocks);
+ if (ret) {
+ dev_err(reset->dev, "Failed to prepare clocks\n");
+ return ret;
+ }
+
+ switch (id) {
+ case IMX8MQ_RESET_VPU_RESET_G1:
+ return regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G1, RESET_G1);
+ case IMX8MQ_RESET_VPU_RESET_G2:
+ return regmap_update_bits(reset->regmap, CTRL_SOFT_RESET, RESET_G2, RESET_G2);
+ }
+
+ clk_bulk_disable_unprepare(reset->num_clocks, reset->clocks);
+
+ return -EINVAL;
+}
+
+static int imx8mq_vpu_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = imx8mq_vpu_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ udelay(2);
+
+ return imx8mq_vpu_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops imx8mq_vpu_reset_ops = {
+ .reset = imx8mq_vpu_reset_dev,
+ .assert = imx8mq_vpu_reset_assert,
+ .deassert = imx8mq_vpu_reset_deassert,
+};
+
+static int imx8mq_vpu_reset_probe(struct platform_device *pdev)
+{
+ struct imx8mq_vpu_reset *reset;
+ struct device *dev = &pdev->dev;
+ struct regmap_config config = { .name = "vpu-reset" };
+
+ reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL);
+ if (!reset)
+ return -ENOMEM;
+
+ reset->regmap = device_node_to_regmap(dev->of_node);
+ if (IS_ERR(reset->regmap)) {
+ dev_err(dev, "Unable to get imx8mq-vpu-reset regmap");
+ return PTR_ERR(reset->regmap);
+ }
+ regmap_attach_dev(dev, reset->regmap, &config);
+
+ reset->num_clocks = devm_clk_bulk_get_all(dev, &reset->clocks);
+ if (!reset->num_clocks)
+ return -EINVAL;
+
+ reset->rcdev.owner = THIS_MODULE;
+ reset->rcdev.nr_resets = 2;
+ reset->rcdev.ops = &imx8mq_vpu_reset_ops;
+ reset->rcdev.of_node = dev->of_node;
+ reset->dev = dev;
+
+ return devm_reset_controller_register(dev, &reset->rcdev);
+}
+
+static const struct of_device_id imx8mq_vpu_reset_dt_ids[] = {
+ { .compatible = "fsl,imx8mq-vpu-reset",},
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx8mq_vpu_reset_dt_ids);
+
+static struct platform_driver imx8mq_vpu_reset_driver = {
+ .probe = imx8mq_vpu_reset_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = imx8mq_vpu_reset_dt_ids,
+ },
+};
+module_platform_driver(imx8mq_vpu_reset_driver);
+
+MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@collabora.com>");
+MODULE_DESCRIPTION("NXP i.MX8MQ VPU reset driver");
+MODULE_LICENSE("GPL v2");
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-02-26 9:14 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-26 9:11 [PATCH v2 0/5] Reset driver for IMX8MQ VPU hardware block Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` [PATCH v2 1/5] dt-bindings: reset: IMX8MQ VPU reset Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` [PATCH v2 2/5] dt-bindings: media: IMX8MQ VPU: document reset usage Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-03-01 14:44 ` Rob Herring
2021-03-01 14:44 ` Rob Herring
2021-03-01 14:44 ` Rob Herring
2021-03-01 14:44 ` Rob Herring
2021-02-26 9:11 ` Benjamin Gaignard [this message]
2021-02-26 9:11 ` [PATCH v2 3/5] reset: Add reset driver for IMX8MQ VPU block Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` [PATCH v2 4/5] media: hantro: Use reset driver Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` [PATCH v2 5/5] arm64: dts: imx8mq: Use reset driver for VPU hardware block Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
2021-02-26 9:11 ` Benjamin Gaignard
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210226091128.14379-4-benjamin.gaignard@collabora.com \
--to=benjamin.gaignard@collabora.com \
--cc=devel@driverdev.osuosl.org \
--cc=devicetree@vger.kernel.org \
--cc=ezequiel@collabora.com \
--cc=festevam@gmail.com \
--cc=gregkh@linuxfoundation.org \
--cc=kernel@collabora.com \
--cc=kernel@pengutronix.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-media@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=mchehab@kernel.org \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=shawnguo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.