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From: Andrew Jeffery <andrew@aj.id.au>
To: qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, ryan_chen@aspeedtech.com,
	minyard@acm.org, qemu-devel@nongnu.org, f4bug@amsat.org,
	clg@kaod.org, joel@jms.id.au
Subject: [PATCH v3 2/5] hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet
Date: Tue,  2 Mar 2021 12:13:14 +1030	[thread overview]
Message-ID: <20210302014317.915120-3-andrew@aj.id.au> (raw)
In-Reply-To: <20210302014317.915120-1-andrew@aj.id.au>

The datasheet says we have 197 IRQs allocated, and we need more than 128
to describe IRQs from LPC devices. Raise the value now to allow
modelling of the LPC devices.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_ast2600.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index bc0eeb058b24..22fcb5b0edbe 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -65,7 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
 
 #define ASPEED_A7MPCORE_ADDR 0x40460000
 
-#define AST2600_MAX_IRQ 128
+#define AST2600_MAX_IRQ 197
 
 /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
 static const int aspeed_soc_ast2600_irqmap[] = {
-- 
2.27.0



  parent reply	other threads:[~2021-03-02  1:47 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-02  1:43 [PATCH v3 0/5] aspeed: LPC peripheral controller devices Andrew Jeffery
2021-03-02  1:43 ` [PATCH v3 1/5] hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC Andrew Jeffery
2021-03-02  1:43 ` Andrew Jeffery [this message]
2021-03-02  1:43 ` [PATCH v3 3/5] hw/arm: ast2600: Correct the iBT interrupt ID Andrew Jeffery
2021-03-02  1:43 ` [PATCH v3 4/5] hw/misc: Add a basic Aspeed LPC controller model Andrew Jeffery
2021-03-02  1:43 ` [PATCH v3 5/5] hw/misc: Model KCS devices in the Aspeed LPC controller Andrew Jeffery

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