From: Nava kishore Manne <nava.manne@xilinx.com> To: <mdf@kernel.org>, <trix@redhat.com>, <robh+dt@kernel.org>, <michal.simek@xilinx.com>, <gregkh@linuxfoundation.org>, <jolly.shah@xilinx.com>, <rajan.vaja@xilinx.com>, <arnd@arndb.de>, <manish.narani@xilinx.com>, <amit.sunil.dhamne@xilinx.com>, <tejas.patel@xilinx.com>, <linux-fpga@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <chinnikishore369@gmail.com> Cc: Nava kishore Manne <nava.manne@xilinx.com>, Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Subject: [PATCH v3 3/3] fpga: versal-fpga: Add versal fpga manager driver Date: Thu, 4 Mar 2021 12:32:24 +0530 [thread overview] Message-ID: <20210304070224.22346-4-nava.manne@xilinx.com> (raw) In-Reply-To: <20210304070224.22346-1-nava.manne@xilinx.com> Add support for Xilinx Versal FPGA manager. PDI source type can be DDR, OCM, QSPI flash etc.. But driver allocates memory always from DDR, Since driver supports only DDR source type. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> --- Changes for v2: -Updated the Fpga Mgr registrations call's to 5.11 -Fixed some minor coding issues as suggested by Moritz. Changes for v3: -Rewritten the Versal fpga Kconfig contents. drivers/fpga/Kconfig | 9 +++ drivers/fpga/Makefile | 1 + drivers/fpga/versal-fpga.c | 117 +++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) create mode 100644 drivers/fpga/versal-fpga.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index bf85b9a65ec2..c1603c7e1518 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -223,4 +223,13 @@ config FPGA_MGR_ZYNQMP_FPGA to configure the programmable logic(PL) through PS on ZynqMP SoC. +config FPGA_MGR_VERSAL_FPGA + tristate "Xilinx Versal FPGA" + depends on ARCH_ZYNQMP || COMPILE_TEST + help + Select this option to enable FPGA manager driver support for + Xilinx Versal SoC. This driver uses the firmware interface to + configure the programmable logic(PL). + + To compile this as a module, choose M here. endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index d8e21dfc6778..40c9adb6a644 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c new file mode 100644 index 000000000000..5744e44f981d --- /dev/null +++ b/drivers/fpga/versal-fpga.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2021 Xilinx, Inc. + */ + +#include <linux/dma-mapping.h> +#include <linux/fpga/fpga-mgr.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/string.h> +#include <linux/firmware/xlnx-zynqmp.h> + +/** + * struct versal_fpga_priv - Private data structure + * @dev: Device data structure + */ +struct versal_fpga_priv { + struct device *dev; +}; + +static int versal_fpga_ops_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t size) +{ + return 0; +} + +static int versal_fpga_ops_write(struct fpga_manager *mgr, + const char *buf, size_t size) +{ + struct versal_fpga_priv *priv; + dma_addr_t dma_addr = 0; + char *kbuf; + int ret; + + priv = mgr->priv; + + kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + memcpy(kbuf, buf, size); + + wmb(); /* ensure all writes are done before initiate FW call */ + + ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr); + + dma_free_coherent(priv->dev, size, kbuf, dma_addr); + + return ret; +} + +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + return 0; +} + +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr) +{ + return FPGA_MGR_STATE_UNKNOWN; +} + +static const struct fpga_manager_ops versal_fpga_ops = { + .state = versal_fpga_ops_state, + .write_init = versal_fpga_ops_write_init, + .write = versal_fpga_ops_write, + .write_complete = versal_fpga_ops_write_complete, +}; + +static int versal_fpga_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct versal_fpga_priv *priv; + struct fpga_manager *mgr; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret < 0) { + dev_err(dev, "no usable DMA configuration\n"); + return ret; + } + + mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager", + &versal_fpga_ops, priv); + if (!mgr) + return -ENOMEM; + + return devm_fpga_mgr_register(dev, mgr); +} + +static const struct of_device_id versal_fpga_of_match[] = { + { .compatible = "xlnx,versal-fpga", }, + {}, +}; +MODULE_DEVICE_TABLE(of, versal_fpga_of_match); + +static struct platform_driver versal_fpga_driver = { + .probe = versal_fpga_probe, + .driver = { + .name = "versal_fpga_manager", + .of_match_table = of_match_ptr(versal_fpga_of_match), + }, +}; +module_platform_driver(versal_fpga_driver); + +MODULE_AUTHOR("Nava kishore Manne <nava.manne@xilinx.com>"); +MODULE_AUTHOR("Appana Durga Kedareswara rao <appanad.durga.rao@xilinx.com>"); +MODULE_DESCRIPTION("Xilinx Versal FPGA Manager"); +MODULE_LICENSE("GPL"); -- 2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Nava kishore Manne <nava.manne@xilinx.com> To: <mdf@kernel.org>, <trix@redhat.com>, <robh+dt@kernel.org>, <michal.simek@xilinx.com>, <gregkh@linuxfoundation.org>, <jolly.shah@xilinx.com>, <rajan.vaja@xilinx.com>, <arnd@arndb.de>, <manish.narani@xilinx.com>, <amit.sunil.dhamne@xilinx.com>, <tejas.patel@xilinx.com>, <linux-fpga@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <chinnikishore369@gmail.com> Cc: Nava kishore Manne <nava.manne@xilinx.com>, Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Subject: [PATCH v3 3/3] fpga: versal-fpga: Add versal fpga manager driver Date: Thu, 4 Mar 2021 12:32:24 +0530 [thread overview] Message-ID: <20210304070224.22346-4-nava.manne@xilinx.com> (raw) In-Reply-To: <20210304070224.22346-1-nava.manne@xilinx.com> Add support for Xilinx Versal FPGA manager. PDI source type can be DDR, OCM, QSPI flash etc.. But driver allocates memory always from DDR, Since driver supports only DDR source type. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> --- Changes for v2: -Updated the Fpga Mgr registrations call's to 5.11 -Fixed some minor coding issues as suggested by Moritz. Changes for v3: -Rewritten the Versal fpga Kconfig contents. drivers/fpga/Kconfig | 9 +++ drivers/fpga/Makefile | 1 + drivers/fpga/versal-fpga.c | 117 +++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) create mode 100644 drivers/fpga/versal-fpga.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index bf85b9a65ec2..c1603c7e1518 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -223,4 +223,13 @@ config FPGA_MGR_ZYNQMP_FPGA to configure the programmable logic(PL) through PS on ZynqMP SoC. +config FPGA_MGR_VERSAL_FPGA + tristate "Xilinx Versal FPGA" + depends on ARCH_ZYNQMP || COMPILE_TEST + help + Select this option to enable FPGA manager driver support for + Xilinx Versal SoC. This driver uses the firmware interface to + configure the programmable logic(PL). + + To compile this as a module, choose M here. endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index d8e21dfc6778..40c9adb6a644 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c new file mode 100644 index 000000000000..5744e44f981d --- /dev/null +++ b/drivers/fpga/versal-fpga.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2021 Xilinx, Inc. + */ + +#include <linux/dma-mapping.h> +#include <linux/fpga/fpga-mgr.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/string.h> +#include <linux/firmware/xlnx-zynqmp.h> + +/** + * struct versal_fpga_priv - Private data structure + * @dev: Device data structure + */ +struct versal_fpga_priv { + struct device *dev; +}; + +static int versal_fpga_ops_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t size) +{ + return 0; +} + +static int versal_fpga_ops_write(struct fpga_manager *mgr, + const char *buf, size_t size) +{ + struct versal_fpga_priv *priv; + dma_addr_t dma_addr = 0; + char *kbuf; + int ret; + + priv = mgr->priv; + + kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + memcpy(kbuf, buf, size); + + wmb(); /* ensure all writes are done before initiate FW call */ + + ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr); + + dma_free_coherent(priv->dev, size, kbuf, dma_addr); + + return ret; +} + +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + return 0; +} + +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr) +{ + return FPGA_MGR_STATE_UNKNOWN; +} + +static const struct fpga_manager_ops versal_fpga_ops = { + .state = versal_fpga_ops_state, + .write_init = versal_fpga_ops_write_init, + .write = versal_fpga_ops_write, + .write_complete = versal_fpga_ops_write_complete, +}; + +static int versal_fpga_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct versal_fpga_priv *priv; + struct fpga_manager *mgr; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret < 0) { + dev_err(dev, "no usable DMA configuration\n"); + return ret; + } + + mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager", + &versal_fpga_ops, priv); + if (!mgr) + return -ENOMEM; + + return devm_fpga_mgr_register(dev, mgr); +} + +static const struct of_device_id versal_fpga_of_match[] = { + { .compatible = "xlnx,versal-fpga", }, + {}, +}; +MODULE_DEVICE_TABLE(of, versal_fpga_of_match); + +static struct platform_driver versal_fpga_driver = { + .probe = versal_fpga_probe, + .driver = { + .name = "versal_fpga_manager", + .of_match_table = of_match_ptr(versal_fpga_of_match), + }, +}; +module_platform_driver(versal_fpga_driver); + +MODULE_AUTHOR("Nava kishore Manne <nava.manne@xilinx.com>"); +MODULE_AUTHOR("Appana Durga Kedareswara rao <appanad.durga.rao@xilinx.com>"); +MODULE_DESCRIPTION("Xilinx Versal FPGA Manager"); +MODULE_LICENSE("GPL"); -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-03-04 7:12 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-04 7:02 [PATCH v3 0/3] Add Bitstream configuration support for Versal Nava kishore Manne 2021-03-04 7:02 ` Nava kishore Manne 2021-03-04 7:02 ` [PATCH v3 1/3] drivers: firmware: Add PDI load API support Nava kishore Manne 2021-03-04 7:02 ` Nava kishore Manne 2021-03-04 7:02 ` [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga manager Nava kishore Manne 2021-03-04 7:02 ` Nava kishore Manne 2021-03-08 20:19 ` Rob Herring 2021-03-08 20:19 ` Rob Herring 2021-03-10 10:49 ` Nava kishore Manne 2021-03-10 10:49 ` Nava kishore Manne 2021-03-10 17:12 ` Rob Herring 2021-03-10 17:12 ` Rob Herring 2021-03-10 17:19 ` Rob Herring 2021-03-10 17:19 ` Rob Herring 2021-04-15 6:07 ` Nava kishore Manne 2021-04-15 6:07 ` Nava kishore Manne 2021-03-04 7:02 ` Nava kishore Manne [this message] 2021-03-04 7:02 ` [PATCH v3 3/3] fpga: versal-fpga: Add versal fpga manager driver Nava kishore Manne
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