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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: sboyd@kernel.org
Cc: robh+dt@kernel.org, john@phrozen.org, tsbogend@alpha.franken.de,
	gregkh@linuxfoundation.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-mips@vger.kernel.org,
	devel@driverdev.osuosl.org, neil@brown.name,
	linux-kernel@vger.kernel.org, Rob Herring <robh@kernel.org>
Subject: [PATCH v11 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks
Date: Tue,  9 Mar 2021 06:22:21 +0100	[thread overview]
Message-ID: <20210309052226.29531-2-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20210309052226.29531-1-sergio.paracuellos@gmail.com>

Adds dt binding header for 'mediatek,mt7621-clk' clocks.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 include/dt-bindings/clock/mt7621-clk.h | 41 ++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index 000000000000..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL		0
+#define MT7621_CLK_CPU		1
+#define MT7621_CLK_BUS		2
+#define MT7621_CLK_50M		3
+#define MT7621_CLK_125M		4
+#define MT7621_CLK_150M		5
+#define MT7621_CLK_250M		6
+#define MT7621_CLK_270M		7
+
+#define MT7621_CLK_HSDMA	8
+#define MT7621_CLK_FE		9
+#define MT7621_CLK_SP_DIVTX	10
+#define MT7621_CLK_TIMER	11
+#define MT7621_CLK_PCM		12
+#define MT7621_CLK_PIO		13
+#define MT7621_CLK_GDMA		14
+#define MT7621_CLK_NAND		15
+#define MT7621_CLK_I2C		16
+#define MT7621_CLK_I2S		17
+#define MT7621_CLK_SPI		18
+#define MT7621_CLK_UART1	19
+#define MT7621_CLK_UART2	20
+#define MT7621_CLK_UART3	21
+#define MT7621_CLK_ETH		22
+#define MT7621_CLK_PCIE0	23
+#define MT7621_CLK_PCIE1	24
+#define MT7621_CLK_PCIE2	25
+#define MT7621_CLK_CRYPTO	26
+#define MT7621_CLK_SHXC		27
+
+#define MT7621_CLK_MAX		28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: sboyd@kernel.org
Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org,
	tsbogend@alpha.franken.de, Rob Herring <robh@kernel.org>,
	gregkh@linuxfoundation.org, linux-mips@vger.kernel.org,
	linux-kernel@vger.kernel.org, robh+dt@kernel.org,
	john@phrozen.org, neil@brown.name, linux-clk@vger.kernel.org
Subject: [PATCH v11 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks
Date: Tue,  9 Mar 2021 06:22:21 +0100	[thread overview]
Message-ID: <20210309052226.29531-2-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20210309052226.29531-1-sergio.paracuellos@gmail.com>

Adds dt binding header for 'mediatek,mt7621-clk' clocks.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 include/dt-bindings/clock/mt7621-clk.h | 41 ++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 include/dt-bindings/clock/mt7621-clk.h

diff --git a/include/dt-bindings/clock/mt7621-clk.h b/include/dt-bindings/clock/mt7621-clk.h
new file mode 100644
index 000000000000..1422badcf9de
--- /dev/null
+++ b/include/dt-bindings/clock/mt7621-clk.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7621_H
+#define _DT_BINDINGS_CLK_MT7621_H
+
+#define MT7621_CLK_XTAL		0
+#define MT7621_CLK_CPU		1
+#define MT7621_CLK_BUS		2
+#define MT7621_CLK_50M		3
+#define MT7621_CLK_125M		4
+#define MT7621_CLK_150M		5
+#define MT7621_CLK_250M		6
+#define MT7621_CLK_270M		7
+
+#define MT7621_CLK_HSDMA	8
+#define MT7621_CLK_FE		9
+#define MT7621_CLK_SP_DIVTX	10
+#define MT7621_CLK_TIMER	11
+#define MT7621_CLK_PCM		12
+#define MT7621_CLK_PIO		13
+#define MT7621_CLK_GDMA		14
+#define MT7621_CLK_NAND		15
+#define MT7621_CLK_I2C		16
+#define MT7621_CLK_I2S		17
+#define MT7621_CLK_SPI		18
+#define MT7621_CLK_UART1	19
+#define MT7621_CLK_UART2	20
+#define MT7621_CLK_UART3	21
+#define MT7621_CLK_ETH		22
+#define MT7621_CLK_PCIE0	23
+#define MT7621_CLK_PCIE1	24
+#define MT7621_CLK_PCIE2	25
+#define MT7621_CLK_CRYPTO	26
+#define MT7621_CLK_SHXC		27
+
+#define MT7621_CLK_MAX		28
+
+#endif /* _DT_BINDINGS_CLK_MT7621_H */
-- 
2.25.1

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  reply	other threads:[~2021-03-09  5:23 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-09  5:22 [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621 Sergio Paracuellos
2021-03-09  5:22 ` Sergio Paracuellos
2021-03-09  5:22 ` Sergio Paracuellos [this message]
2021-03-09  5:22   ` [PATCH v11 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks Sergio Paracuellos
2021-04-09 18:15   ` Stephen Boyd
2021-04-09 18:15     ` Stephen Boyd
2021-03-09  5:22 ` [PATCH v11 2/6] dt: bindings: add mt7621-sysc device tree binding documentation Sergio Paracuellos
2021-03-09  5:22   ` Sergio Paracuellos
2021-04-09 18:15   ` Stephen Boyd
2021-04-09 18:15     ` Stephen Boyd
2021-03-09  5:22 ` [PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC Sergio Paracuellos
2021-03-09  5:22   ` Sergio Paracuellos
2021-04-09 18:14   ` Stephen Boyd
2021-04-09 18:14     ` Stephen Boyd
2021-04-09 18:34     ` Sergio Paracuellos
2021-04-09 18:34       ` Sergio Paracuellos
2021-04-09 18:38       ` Stephen Boyd
2021-03-09  5:22 ` [PATCH v11 4/6] staging: mt7621-dts: make use of new 'mt7621-clk' Sergio Paracuellos
2021-03-09  5:22   ` Sergio Paracuellos
2021-03-09  5:22 ` [PATCH v11 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk' Sergio Paracuellos
2021-03-09  5:22   ` Sergio Paracuellos
2021-03-09 15:07   ` Thomas Bogendoerfer
2021-03-09 15:07     ` Thomas Bogendoerfer
2021-03-09  5:22 ` [PATCH v11 6/6] MAINTAINERS: add MT7621 CLOCK maintainer Sergio Paracuellos
2021-03-09  5:22   ` Sergio Paracuellos
2021-03-23  8:13 ` [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621 Sergio Paracuellos
2021-03-23  8:13   ` Sergio Paracuellos
2021-04-09 18:17   ` Stephen Boyd
2021-04-09 18:25     ` Sergio Paracuellos
2021-04-09 18:31       ` Stephen Boyd

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