From: Vijai Kumar K <vijai@behindbytes.com> To: qemu-riscv@nongnu.org Cc: Vijai Kumar K <vijai@behindbytes.com>, qemu-devel@nongnu.org Subject: [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform Date: Sun, 14 Mar 2021 14:09:36 +0530 [thread overview] Message-ID: <20210314083936.76269-4-vijai@behindbytes.com> (raw) In-Reply-To: <20210314083936.76269-1-vijai@behindbytes.com> Connect one shakti uart to the shakti_c machine. Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> --- hw/riscv/shakti_c.c | 7 +++++++ include/hw/riscv/shakti_c.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index e96436a3bf..07cc42a380 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -133,6 +133,12 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp) shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, SIFIVE_CLINT_TIMEBASE_FREQ, false); + qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); + if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0, + shakti_c_memmap[SHAKTI_C_UART].base); /* ROM */ memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal); @@ -151,6 +157,7 @@ static void shakti_c_soc_instance_init(Object *obj) ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj); object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY); + object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART); /* * CPU type is fixed and we are not supporting passing from commandline yet. diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h index 6c66a160f5..3abb080d3c 100644 --- a/include/hw/riscv/shakti_c.h +++ b/include/hw/riscv/shakti_c.h @@ -21,6 +21,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/boards.h" +#include "hw/char/shakti_uart.h" #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" #define RISCV_SHAKTI_SOC(obj) \ @@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState { /*< public >*/ RISCVHartArrayState cpus; DeviceState *plic; + ShaktiUartState uart; MemoryRegion rom; } ShaktiCSoCState; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Vijai Kumar K <vijai@behindbytes.com> To: qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Vijai Kumar K <vijai@behindbytes.com> Subject: [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform Date: Sun, 14 Mar 2021 14:09:36 +0530 [thread overview] Message-ID: <20210314083936.76269-4-vijai@behindbytes.com> (raw) In-Reply-To: <20210314083936.76269-1-vijai@behindbytes.com> Connect one shakti uart to the shakti_c machine. Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> --- hw/riscv/shakti_c.c | 7 +++++++ include/hw/riscv/shakti_c.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index e96436a3bf..07cc42a380 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -133,6 +133,12 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp) shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, SIFIVE_CLINT_TIMEBASE_FREQ, false); + qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0)); + if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0, + shakti_c_memmap[SHAKTI_C_UART].base); /* ROM */ memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom", shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal); @@ -151,6 +157,7 @@ static void shakti_c_soc_instance_init(Object *obj) ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj); object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY); + object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART); /* * CPU type is fixed and we are not supporting passing from commandline yet. diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h index 6c66a160f5..3abb080d3c 100644 --- a/include/hw/riscv/shakti_c.h +++ b/include/hw/riscv/shakti_c.h @@ -21,6 +21,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/boards.h" +#include "hw/char/shakti_uart.h" #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc" #define RISCV_SHAKTI_SOC(obj) \ @@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState { /*< public >*/ RISCVHartArrayState cpus; DeviceState *plic; + ShaktiUartState uart; MemoryRegion rom; } ShaktiCSoCState; -- 2.25.1
next prev parent reply other threads:[~2021-03-14 9:12 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-14 8:39 [PATCH 0/3] Add support for Shakti SoC from IIT-M Vijai Kumar K 2021-03-14 8:39 ` Vijai Kumar K 2021-03-14 8:39 ` [PATCH 1/3] riscv: Add initial support for Shakti C class Vijai Kumar K 2021-03-14 8:39 ` Vijai Kumar K 2021-03-19 13:39 ` Alistair Francis 2021-03-20 9:46 ` Vijai Kumar K 2021-03-14 8:39 ` [PATCH 2/3] hw/char: Add Shakti UART emulation Vijai Kumar K 2021-03-14 8:39 ` Vijai Kumar K 2021-03-19 13:44 ` Alistair Francis 2021-03-20 9:41 ` Vijai Kumar K 2021-03-14 8:39 ` Vijai Kumar K [this message] 2021-03-14 8:39 ` [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform Vijai Kumar K 2021-03-19 13:47 ` Alistair Francis 2021-03-20 9:38 ` Vijai Kumar K
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