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From: Rebecca Cran <rebecca@nuviainc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	qemu-arm@nongnu.org
Cc: Rebecca Cran <rebecca@nuviainc.com>, qemu-devel@nongnu.org
Subject: [PATCH v4 0/3] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE
Date: Tue, 16 Mar 2021 09:49:07 -0600	[thread overview]
Message-ID: <20210316154910.25804-1-rebecca@nuviainc.com> (raw)

ARMv8.4 adds the mandatory FEAT_TLBIOS and FEAT_TLBIRANGE. 
They provides TLBI maintenance instructions that extend to the Outer
Shareable domain and that apply to a range of input addresses.

Changes from v3 to v4:

o Adapted code from the existing flush_page_bits_* functions to support
  flushing a range of addresses.
o Changed the API from num_pages to length.
o Removed the exception generation from tlbi_aa64_range_get_num_pages.
o The addr is no longer passed into tlbi_aa64_range_get_num_pages.
o Other changes based on feedback.

Rebecca Cran (3):
  target/arm: Add support for FEAT_TLBIRANGE
  target/arm: Add support for FEAT_TLBIOS
  target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type

 accel/tcg/cputlb.c      | 135 +++++++
 include/exec/exec-all.h |  45 +++
 target/arm/cpu.h        |  10 +
 target/arm/cpu64.c      |   1 +
 target/arm/helper.c     | 393 ++++++++++++++++++++
 5 files changed, 584 insertions(+)

-- 
2.26.2



             reply	other threads:[~2021-03-16 15:53 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-16 15:49 Rebecca Cran [this message]
2021-03-16 15:49 ` [PATCH v4 1/3] target/arm: Add support for FEAT_TLBIRANGE Rebecca Cran
2021-03-16 18:09   ` Richard Henderson
2021-03-16 21:13     ` Rebecca Cran
2021-03-16 15:49 ` [PATCH v4 2/3] target/arm: Add support for FEAT_TLBIOS Rebecca Cran
2021-03-16 15:49 ` [PATCH v4 3/3] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type Rebecca Cran
2021-03-16 17:03 ` [PATCH v4 0/3] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE no-reply

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