From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
Date: Fri, 19 Mar 2021 16:30:19 +0200 [thread overview]
Message-ID: <20210319143021.21823-1-ville.syrjala@linux.intel.com> (raw)
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We've defined C0DRB3/C0DRB3 as 16 bit registers, so access them
as such.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index e891552611d5..e889a76c85c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -642,8 +642,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
* banks of memory are paired and unswizzled on the
* uneven portion, so leave that as unknown.
*/
- if (intel_uncore_read(uncore, C0DRB3) ==
- intel_uncore_read(uncore, C1DRB3)) {
+ if (intel_uncore_read16(uncore, C0DRB3) ==
+ intel_uncore_read16(uncore, C1DRB3)) {
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
}
--
2.26.2
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next reply other threads:[~2021-03-19 14:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-19 14:30 Ville Syrjala [this message]
2021-03-19 14:30 ` [Intel-gfx] [PATCH 2/3] drm/i915: Give C0DRB3/C1DRB3 a _BW suffix Ville Syrjala
2021-03-19 14:30 ` [Intel-gfx] [PATCH 3/3] drm/i915: Rewrite CL/CTG L-shaped memory detection Ville Syrjala
2021-03-19 15:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again Patchwork
2021-03-19 18:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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