All of lore.kernel.org
 help / color / mirror / Atom feed
From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Cc: alistair23@gmail.com, Bin Meng <bmeng.cn@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	qemu-devel@nongnu.org, Asherah Connor <ashe@kivikakk.ee>
Subject: [PULL 09/16] hw/riscv: Add fw_cfg support to virt
Date: Mon, 22 Mar 2021 21:57:49 -0400	[thread overview]
Message-ID: <20210323015756.3168650-10-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210323015756.3168650-1-alistair.francis@wdc.com>

From: Asherah Connor <ashe@kivikakk.ee>

Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  2 ++
 hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig        |  1 +
 3 files changed, 33 insertions(+)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 632da52018..349fee1f89 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -40,6 +40,7 @@ struct RISCVVirtState {
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
+    FWCfgState *fw_cfg;
 
     int fdt_size;
 };
@@ -53,6 +54,7 @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
+    VIRT_FW_CFG,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 0b39101a5e..e96ec4cbbc 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -53,6 +53,7 @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -507,6 +508,28 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
+static FWCfgState *create_fw_cfg(const MachineState *mc)
+{
+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+    FWCfgState *fw_cfg;
+    char *nodename;
+
+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+                                  &address_space_memory);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(mc->fdt, nodename);
+    qemu_fdt_setprop_string(mc->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+    return fw_cfg;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -688,6 +711,13 @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, machine->fdt);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index d139074b02..1de18cdcf1 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -33,6 +33,7 @@ config RISCV_VIRT
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
+    select FW_CFG_DMA
 
 config SIFIVE_E
     bool
-- 
2.30.1



  parent reply	other threads:[~2021-03-23  2:14 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-23  1:57 [PULL 00/16] riscv-to-apply queue Alistair Francis
2021-03-23  1:57 ` [PULL 01/16] target/riscv: fix vs() to return proper error code Alistair Francis
2021-03-23  1:57 ` [PULL 02/16] hw/char: disable ibex uart receive if the buffer is full Alistair Francis
2021-03-23  1:57 ` [PULL 03/16] target/riscv: propagate PMP permission to TLB page Alistair Francis
2021-03-23  1:57 ` [PULL 04/16] target/riscv: add log of PMP permission checking Alistair Francis
2021-03-23  1:57 ` [PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed Alistair Francis
2021-03-23  1:57 ` [PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions Alistair Francis
2021-03-23  1:57 ` [PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip Alistair Francis
2021-03-23  1:57 ` [PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV Alistair Francis
2021-03-23  1:57 ` Alistair Francis [this message]
2021-03-23  1:57 ` [PULL 10/16] hw/riscv: allow ramfb on virt Alistair Francis
2021-03-23  1:57 ` [PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie Alistair Francis
2021-03-23  1:57 ` [PULL 12/16] target/riscv: Add proper two-stage lookup exception detection Alistair Francis
2021-03-23  1:57 ` [PULL 13/16] hw/block: m25p80: Support fast read for SST flashes Alistair Francis
2021-03-23  1:57 ` [PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register Alistair Francis
2021-03-23  1:57 ` [PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine Alistair Francis
2021-03-23  1:57 ` [PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions Alistair Francis
2021-03-23 16:48 ` [PULL 00/16] riscv-to-apply queue Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210323015756.3168650-10-alistair.francis@wdc.com \
    --to=alistair.francis@wdc.com \
    --cc=alistair23@gmail.com \
    --cc=ashe@kivikakk.ee \
    --cc=bmeng.cn@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.