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From: chun-jie.chen <chun-jie.chen@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh@kernel.org>,  Stephen Boyd <sboyd@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
	<srv_heupstream@mediatek.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	chun-jie.chen <chun-jie.chen@mediatek.com>,
	Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [RESEND PATCH v7 09/22] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers
Date: Wed, 24 Mar 2021 18:40:57 +0800	[thread overview]
Message-ID: <20210324104110.13383-10-chun-jie.chen@mediatek.com> (raw)
In-Reply-To: <20210324104110.13383-1-chun-jie.chen@mediatek.com>

Most of subsystem clock providers only need to register clock gates
in their probe() function.
To reduce the duplicated code by add a generic function.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mtk.c | 23 +++++++++++++++++++++++
 drivers/clk/mediatek/clk-mtk.h |  8 ++++++++
 2 files changed, 31 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index cec1c8a27211..67693b7d66b5 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -13,6 +13,7 @@
 #include <linux/clkdev.h>
 #include <linux/mfd/syscon.h>
 #include <linux/device.h>
+#include <linux/of_device.h>
 
 #include "clk-mtk.h"
 #include "clk-gate.h"
@@ -286,3 +287,25 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
 			clk_data->clks[mcd->id] = clk;
 	}
 }
+
+int mtk_clk_simple_probe(struct platform_device *pdev)
+{
+	const struct mtk_clk_desc *mcd;
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+
+	mcd = of_device_get_match_data(&pdev->dev);
+	if (!mcd)
+		return -EINVAL;
+
+	clk_data = mtk_alloc_clk_data(mcd->num_clks);
+	if (!clk_data)
+		return -ENOMEM;
+
+	r = mtk_clk_register_gates(node, mcd->clks, mcd->num_clks, clk_data);
+	if (r)
+		return r;
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 31c7cb304508..7de41c3b3206 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -10,6 +10,7 @@
 #include <linux/regmap.h>
 #include <linux/bitops.h>
 #include <linux/clk-provider.h>
+#include <linux/platform_device.h>
 
 struct clk;
 struct clk_onecell_data;
@@ -250,4 +251,11 @@ void mtk_register_reset_controller(struct device_node *np,
 void mtk_register_reset_controller_set_clr(struct device_node *np,
 	unsigned int num_regs, int regofs);
 
+struct mtk_clk_desc {
+	const struct mtk_gate *clks;
+	size_t num_clks;
+};
+
+int mtk_clk_simple_probe(struct platform_device *pdev);
+
 #endif /* __DRV_CLK_MTK_H */
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: chun-jie.chen <chun-jie.chen@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh@kernel.org>,  Stephen Boyd <sboyd@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
	<srv_heupstream@mediatek.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	chun-jie.chen <chun-jie.chen@mediatek.com>,
	Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [RESEND PATCH v7 09/22] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers
Date: Wed, 24 Mar 2021 18:40:57 +0800	[thread overview]
Message-ID: <20210324104110.13383-10-chun-jie.chen@mediatek.com> (raw)
In-Reply-To: <20210324104110.13383-1-chun-jie.chen@mediatek.com>

Most of subsystem clock providers only need to register clock gates
in their probe() function.
To reduce the duplicated code by add a generic function.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com>
---
 drivers/clk/mediatek/clk-mtk.c | 23 +++++++++++++++++++++++
 drivers/clk/mediatek/clk-mtk.h |  8 ++++++++
 2 files changed, 31 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index cec1c8a27211..67693b7d66b5 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -13,6 +13,7 @@
 #include <linux/clkdev.h>
 #include <linux/mfd/syscon.h>
 #include <linux/device.h>
+#include <linux/of_device.h>
 
 #include "clk-mtk.h"
 #include "clk-gate.h"
@@ -286,3 +287,25 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
 			clk_data->clks[mcd->id] = clk;
 	}
 }
+
+int mtk_clk_simple_probe(struct platform_device *pdev)
+{
+	const struct mtk_clk_desc *mcd;
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+
+	mcd = of_device_get_match_data(&pdev->dev);
+	if (!mcd)
+		return -EINVAL;
+
+	clk_data = mtk_alloc_clk_data(mcd->num_clks);
+	if (!clk_data)
+		return -ENOMEM;
+
+	r = mtk_clk_register_gates(node, mcd->clks, mcd->num_clks, clk_data);
+	if (r)
+		return r;
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 31c7cb304508..7de41c3b3206 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -10,6 +10,7 @@
 #include <linux/regmap.h>
 #include <linux/bitops.h>
 #include <linux/clk-provider.h>
+#include <linux/platform_device.h>
 
 struct clk;
 struct clk_onecell_data;
@@ -250,4 +251,11 @@ void mtk_register_reset_controller(struct device_node *np,
 void mtk_register_reset_controller_set_clr(struct device_node *np,
 	unsigned int num_regs, int regofs);
 
+struct mtk_clk_desc {
+	const struct mtk_gate *clks;
+	size_t num_clks;
+};
+
+int mtk_clk_simple_probe(struct platform_device *pdev);
+
 #endif /* __DRV_CLK_MTK_H */
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-03-24 10:51 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-24 10:40 [RESEND PATCH v7 00/22] Mediatek MT8192 clock support chun-jie.chen
2021-03-24 10:40 ` chun-jie.chen
2021-03-24 10:40 ` [RESEND PATCH v7 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller chun-jie.chen
2021-03-24 10:40   ` chun-jie.chen
2021-04-30  1:42   ` Stephen Boyd
2021-04-30  1:42     ` Stephen Boyd
2021-05-05 11:23     ` Chun-Jie Chen
2021-05-05 11:23       ` Chun-Jie Chen
2021-03-24 10:40 ` [RESEND PATCH v7 02/22] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller chun-jie.chen
2021-03-24 10:40   ` chun-jie.chen
2021-03-24 10:40 ` [RESEND PATCH v7 03/22] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller chun-jie.chen
2021-03-24 10:40   ` chun-jie.chen
2021-03-24 10:40 ` [RESEND PATCH v7 04/22] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller chun-jie.chen
2021-03-24 10:40   ` chun-jie.chen
2021-03-24 10:40 ` [RESEND PATCH v7 05/22] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers chun-jie.chen
2021-03-24 10:40   ` chun-jie.chen
2021-03-24 10:40 ` [RESEND PATCH v7 06/22] clk: mediatek: Add dt-bindings of MT8192 clocks chun-jie.chen
2021-03-24 10:40   ` chun-jie.chen
2021-03-24 10:40 ` [RESEND PATCH v7 07/22] clk: mediatek: Fix asymmetrical PLL enable and disable control chun-jie.chen
2021-03-24 10:40   ` chun-jie.chen
2021-03-24 10:40 ` [RESEND PATCH v7 08/22] clk: mediatek: Add configurable enable control to mtk_pll_data chun-jie.chen
2021-03-24 10:40   ` chun-jie.chen
2021-03-24 10:40 ` chun-jie.chen [this message]
2021-03-24 10:40   ` [RESEND PATCH v7 09/22] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers chun-jie.chen
2021-03-24 10:40 ` [RESEND PATCH v7 10/22] clk: mediatek: Add MT8192 basic clocks support chun-jie.chen
2021-03-24 10:40   ` chun-jie.chen
2021-03-24 10:40 ` [RESEND PATCH v7 11/22] clk: mediatek: Add MT8192 audio clock support chun-jie.chen
2021-03-24 10:40   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 12/22] clk: mediatek: Add MT8192 camsys " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 13/22] clk: mediatek: Add MT8192 imgsys " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 14/22] clk: mediatek: Add MT8192 imp i2c wrapper " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 15/22] clk: mediatek: Add MT8192 ipesys " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 16/22] clk: mediatek: Add MT8192 mdpsys " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 17/22] clk: mediatek: Add MT8192 mfgcfg " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 18/22] clk: mediatek: Add MT8192 mmsys " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 19/22] clk: mediatek: Add MT8192 msdc " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 20/22] clk: mediatek: Add MT8192 scp adsp " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 21/22] clk: mediatek: Add MT8192 vdecsys " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-03-24 10:41 ` [RESEND PATCH v7 22/22] clk: mediatek: Add MT8192 vencsys " chun-jie.chen
2021-03-24 10:41   ` chun-jie.chen
2021-04-08 11:28 ` [RESEND PATCH v7 00/22] Mediatek MT8192 " 20181221120906 created
2021-04-08 11:28   ` 20181221120906 created
2021-04-28  6:44   ` Ikjoon Jang
2021-04-28  6:44     ` Ikjoon Jang
2021-04-28  6:44     ` Ikjoon Jang
2021-05-05  6:58     ` Chun-Jie Chen
2021-05-05  6:58       ` Chun-Jie Chen

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