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From: Alain Volmat <avolmat@me.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lee Jones <lee.jones@linaro.org>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Alain Volmat <avolmat@me.com>
Subject: [PATCH v2 13/16] ARM: dts: sti: update clkgen-pll entries in stih418-clock
Date: Thu, 25 Mar 2021 08:50:15 +0100	[thread overview]
Message-ID: <20210325075018.6598-14-avolmat@me.com> (raw)
In-Reply-To: <20210325075018.6598-1-avolmat@me.com>

The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.

Signed-off-by: Alain Volmat <avolmat@me.com>
---
 arch/arm/boot/dts/stih418-clock.dtsi | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 35d12979cdf4..d628e656458d 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -39,8 +39,6 @@
 				compatible = "st,stih418-clkgen-plla9";
 
 				clocks = <&clk_sysin>;
-
-				clock-output-names = "clockgen-a9-pll-odf";
 			};
 		};
 
@@ -75,11 +73,9 @@
 
 			clk_s_a0_pll: clk-s-a0-pll {
 				#clock-cells = <1>;
-				compatible = "st,clkgen-pll0";
+				compatible = "st,clkgen-pll0-a0";
 
 				clocks = <&clk_sysin>;
-
-				clock-output-names = "clk-s-a0-pll-ofd-0";
 			};
 
 			clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -111,20 +107,16 @@
 
 			clk_s_c0_pll0: clk-s-c0-pll0 {
 				#clock-cells = <1>;
-				compatible = "st,clkgen-pll0";
+				compatible = "st,clkgen-pll0-c0";
 
 				clocks = <&clk_sysin>;
-
-				clock-output-names = "clk-s-c0-pll0-odf-0";
 			};
 
 			clk_s_c0_pll1: clk-s-c0-pll1 {
 				#clock-cells = <1>;
-				compatible = "st,clkgen-pll1";
+				compatible = "st,clkgen-pll1-c0";
 
 				clocks = <&clk_sysin>;
-
-				clock-output-names = "clk-s-c0-pll1-odf-0";
 			};
 
 			clk_s_c0_flexgen: clk-s-c0-flexgen {
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Alain Volmat <avolmat@me.com>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Lee Jones <lee.jones@linaro.org>,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Alain Volmat <avolmat@me.com>
Subject: [PATCH v2 13/16] ARM: dts: sti: update clkgen-pll entries in stih418-clock
Date: Thu, 25 Mar 2021 08:50:15 +0100	[thread overview]
Message-ID: <20210325075018.6598-14-avolmat@me.com> (raw)
In-Reply-To: <20210325075018.6598-1-avolmat@me.com>

The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.

Signed-off-by: Alain Volmat <avolmat@me.com>
---
 arch/arm/boot/dts/stih418-clock.dtsi | 14 +++-----------
 1 file changed, 3 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 35d12979cdf4..d628e656458d 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -39,8 +39,6 @@
 				compatible = "st,stih418-clkgen-plla9";
 
 				clocks = <&clk_sysin>;
-
-				clock-output-names = "clockgen-a9-pll-odf";
 			};
 		};
 
@@ -75,11 +73,9 @@
 
 			clk_s_a0_pll: clk-s-a0-pll {
 				#clock-cells = <1>;
-				compatible = "st,clkgen-pll0";
+				compatible = "st,clkgen-pll0-a0";
 
 				clocks = <&clk_sysin>;
-
-				clock-output-names = "clk-s-a0-pll-ofd-0";
 			};
 
 			clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -111,20 +107,16 @@
 
 			clk_s_c0_pll0: clk-s-c0-pll0 {
 				#clock-cells = <1>;
-				compatible = "st,clkgen-pll0";
+				compatible = "st,clkgen-pll0-c0";
 
 				clocks = <&clk_sysin>;
-
-				clock-output-names = "clk-s-c0-pll0-odf-0";
 			};
 
 			clk_s_c0_pll1: clk-s-c0-pll1 {
 				#clock-cells = <1>;
-				compatible = "st,clkgen-pll1";
+				compatible = "st,clkgen-pll1-c0";
 
 				clocks = <&clk_sysin>;
-
-				clock-output-names = "clk-s-c0-pll1-odf-0";
 			};
 
 			clk_s_c0_flexgen: clk-s-c0-flexgen {
-- 
2.17.1


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  parent reply	other threads:[~2021-03-25  7:53 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-25  7:50 [PATCH v2 00/16] clk: st: embed clock outputs within drivers Alain Volmat
2021-03-25  7:50 ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 01/16] clk: st: clkgen-pll: remove used variable of struct clkgen_pll Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 02/16] clk: st: flexgen: embed soc clock outputs within compatible data Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 03/16] dt-bindings: clock: st: flexgen: add new introduced compatible Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-27 17:43   ` Rob Herring
2021-03-27 17:43     ` Rob Herring
2021-03-25  7:50 ` [PATCH v2 04/16] clk: st: clkgen-pll: embed soc clock outputs within compatible data Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 05/16] dt-bindings: clock: st: clkgen-pll: add new introduced compatible Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-27 17:46   ` Rob Herring
2021-03-27 17:46     ` Rob Herring
2021-03-25  7:50 ` [PATCH v2 06/16] clk: st: clkgen-fsyn: embed soc clock outputs within compatible data Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 07/16] dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 08/16] ARM: dts: sti: update flexgen compatible within stih418-clock Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 09/16] ARM: dts: sti: update flexgen compatible within stih407-clock Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 10/16] ARM: dts: sti: update flexgen compatible within stih410-clock Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 11/16] ARM: dts: sti: update clkgen-pll entries in stih407-clock Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 12/16] ARM: dts: sti: update clkgen-pll entries in stih410-clock Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` Alain Volmat [this message]
2021-03-25  7:50   ` [PATCH v2 13/16] ARM: dts: sti: update clkgen-pll entries in stih418-clock Alain Volmat
2021-03-25  7:50 ` [PATCH v2 14/16] ARM: dts: sti: update clkgen-fsyn entries in stih407-clock Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 15/16] ARM: dts: sti: update clkgen-fsyn entries in stih410-clock Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-25  7:50 ` [PATCH v2 16/16] ARM: dts: sti: update clkgen-fsyn entries in stih418-clock Alain Volmat
2021-03-25  7:50   ` Alain Volmat
2021-03-30  2:01 ` [PATCH v2 00/16] clk: st: embed clock outputs within drivers Stephen Boyd
2021-03-30  2:01   ` Stephen Boyd

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