From: Kishon Vijay Abraham I <kishon@ti.com> To: Kishon Vijay Abraham I <kishon@ti.com>, Bjorn Helgaas <bhelgaas@google.com>, Rob Herring <robh+dt@kernel.org>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Marc Zyngier <maz@kernel.org> Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, Lokesh Vutla <lokeshvutla@ti.com> Subject: [PATCH 2/6] dt-bindings: PCI: ti,am65: Add PCIe endpoint mode dt-bindings for TI's AM65 SoC Date: Thu, 25 Mar 2021 14:30:22 +0530 [thread overview] Message-ID: <20210325090026.8843-3-kishon@ti.com> (raw) In-Reply-To: <20210325090026.8843-1-kishon@ti.com> Add PCIe endpoint mode dt-bindings for TI's AM65 SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../bindings/pci/ti,am65-pci-ep.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml new file mode 100644 index 000000000000..f0a5518e6331 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI AM65 PCI Endpoint + +maintainers: + - Kishon Vijay Abraham I <kishon@ti.com> + +allOf: + - $ref: "pci-ep.yaml#" + +properties: + compatible: + enum: + - ti,am654-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: app + - const: dbics + - const: addr_space + - const: atu + + power-domains: + maxItems: 1 + + ti,syscon-pcie-mode: + description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + minItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - reg-names + - max-link-speed + - num-lanes + - power-domains + - ti,syscon-pcie-mode + - phys + - phy-names + - dma-coherent + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/soc/ti,sci_pm_domain.h> + #include <dt-bindings/gpio/gpio.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_ep: pcie-ep@5500000 { + compatible = "ti,am654-pcie-ep"; + reg = <0x0 0x5500000 0x0 0x1000>, + <0x0 0x5501000 0x0 0x1000>, + <0x0 0x10000000 0x0 0x8000000>, + <0x0 0x5506000 0x0 0x1000>; + reg-names = "app", "dbics", "addr_space", "atu"; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + ti,syscon-pcie-mode = <&pcie0_mode>; + num-ib-windows = <16>; + num-ob-windows = <16>; + max-link-speed = <2>; + dma-coherent; + interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; + }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com> To: Kishon Vijay Abraham I <kishon@ti.com>, Bjorn Helgaas <bhelgaas@google.com>, Rob Herring <robh+dt@kernel.org>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Marc Zyngier <maz@kernel.org> Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, Lokesh Vutla <lokeshvutla@ti.com> Subject: [PATCH 2/6] dt-bindings: PCI: ti, am65: Add PCIe endpoint mode dt-bindings for TI's AM65 SoC Date: Thu, 25 Mar 2021 14:30:22 +0530 [thread overview] Message-ID: <20210325090026.8843-3-kishon@ti.com> (raw) In-Reply-To: <20210325090026.8843-1-kishon@ti.com> Add PCIe endpoint mode dt-bindings for TI's AM65 SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../bindings/pci/ti,am65-pci-ep.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml new file mode 100644 index 000000000000..f0a5518e6331 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI AM65 PCI Endpoint + +maintainers: + - Kishon Vijay Abraham I <kishon@ti.com> + +allOf: + - $ref: "pci-ep.yaml#" + +properties: + compatible: + enum: + - ti,am654-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: app + - const: dbics + - const: addr_space + - const: atu + + power-domains: + maxItems: 1 + + ti,syscon-pcie-mode: + description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + minItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - reg-names + - max-link-speed + - num-lanes + - power-domains + - ti,syscon-pcie-mode + - phys + - phy-names + - dma-coherent + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/soc/ti,sci_pm_domain.h> + #include <dt-bindings/gpio/gpio.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie0_ep: pcie-ep@5500000 { + compatible = "ti,am654-pcie-ep"; + reg = <0x0 0x5500000 0x0 0x1000>, + <0x0 0x5501000 0x0 0x1000>, + <0x0 0x10000000 0x0 0x8000000>, + <0x0 0x5506000 0x0 0x1000>; + reg-names = "app", "dbics", "addr_space", "atu"; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + ti,syscon-pcie-mode = <&pcie0_mode>; + num-ib-windows = <16>; + num-ob-windows = <16>; + max-link-speed = <2>; + dma-coherent; + interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; + }; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-03-25 9:01 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-25 9:00 [PATCH 0/6] PCI: Add legacy interrupt support in Keystone Kishon Vijay Abraham I 2021-03-25 9:00 ` Kishon Vijay Abraham I 2021-03-25 9:00 ` [PATCH 1/6] dt-bindings: PCI: ti,am65: Add PCIe host mode dt-bindings for TI's AM65 SoC Kishon Vijay Abraham I 2021-03-25 9:00 ` [PATCH 1/6] dt-bindings: PCI: ti, am65: " Kishon Vijay Abraham I 2021-03-25 16:56 ` Rob Herring 2021-03-25 16:56 ` Rob Herring 2021-03-25 23:38 ` [PATCH 1/6] dt-bindings: PCI: ti,am65: " Rob Herring 2021-03-25 23:38 ` Rob Herring 2021-03-30 9:29 ` Kishon Vijay Abraham I 2021-03-30 9:29 ` Kishon Vijay Abraham I 2021-04-20 13:13 ` Rob Herring 2021-04-20 13:13 ` Rob Herring 2021-03-25 9:00 ` Kishon Vijay Abraham I [this message] 2021-03-25 9:00 ` [PATCH 2/6] dt-bindings: PCI: ti, am65: Add PCIe endpoint " Kishon Vijay Abraham I 2021-03-25 16:56 ` Rob Herring 2021-03-25 16:56 ` Rob Herring 2021-03-25 9:00 ` [PATCH 3/6] irqdomain: Export of_phandle_args_to_fwspec() Kishon Vijay Abraham I 2021-03-25 9:00 ` Kishon Vijay Abraham I 2021-03-25 9:00 ` [PATCH 4/6] PCI: keystone: Convert to using hierarchy domain for legacy interrupts Kishon Vijay Abraham I 2021-03-25 9:00 ` Kishon Vijay Abraham I 2021-03-26 6:58 ` Krzysztof Wilczyński 2021-03-26 6:58 ` Krzysztof Wilczyński 2021-03-25 9:00 ` [PATCH 5/6] PCI: keystone: Add PCI legacy interrupt support for AM654 Kishon Vijay Abraham I 2021-03-25 9:00 ` Kishon Vijay Abraham I 2021-03-26 7:14 ` Krzysztof Wilczyński 2021-03-26 7:14 ` Krzysztof Wilczyński 2021-04-02 11:11 ` Marc Zyngier 2021-04-02 11:11 ` Marc Zyngier 2021-03-25 9:00 ` [PATCH 6/6] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0) Kishon Vijay Abraham I 2021-03-25 9:00 ` Kishon Vijay Abraham I 2021-03-26 7:19 ` Krzysztof Wilczyński 2021-03-26 7:19 ` Krzysztof Wilczyński 2021-05-17 13:15 ` [PATCH 0/6] PCI: Add legacy interrupt support in Keystone Christian Gmeiner 2021-05-17 13:15 ` Christian Gmeiner 2021-05-17 13:21 ` Kishon Vijay Abraham I 2021-05-17 13:21 ` Kishon Vijay Abraham I
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