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From: chun-jie.chen <chun-jie.chen@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh@kernel.org>,
	 Nicolas Boichat <drinkcat@chromium.org>
Cc: <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	chun-jie.chen <chun-jie.chen@mediatek.com>,
	Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v2 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
Date: Wed, 31 Mar 2021 16:38:54 +0800	[thread overview]
Message-ID: <20210331083854.7650-3-chun-jie.chen@mediatek.com> (raw)
In-Reply-To: <20210331083854.7650-1-chun-jie.chen@mediatek.com>

infra_uart0 clock is the real one what uart0 uses as bus clock.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index ffd0fe331bdc..7daa97199dd0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -327,7 +327,7 @@
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11002000 0 0x1000>;
 			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
-			clocks = <&clk26m>, <&clk26m>;
+			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
 			clock-names = "baud", "bus";
 			status = "disabled";
 		};
-- 
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: chun-jie.chen <chun-jie.chen@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh@kernel.org>,
	 Nicolas Boichat <drinkcat@chromium.org>
Cc: <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	chun-jie.chen <chun-jie.chen@mediatek.com>,
	Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v2 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
Date: Wed, 31 Mar 2021 16:38:54 +0800	[thread overview]
Message-ID: <20210331083854.7650-3-chun-jie.chen@mediatek.com> (raw)
In-Reply-To: <20210331083854.7650-1-chun-jie.chen@mediatek.com>

infra_uart0 clock is the real one what uart0 uses as bus clock.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index ffd0fe331bdc..7daa97199dd0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -327,7 +327,7 @@
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11002000 0 0x1000>;
 			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
-			clocks = <&clk26m>, <&clk26m>;
+			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
 			clock-names = "baud", "bus";
 			status = "disabled";
 		};
-- 
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-03-31  8:39 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-31  8:38 [PATCH v2 0/2] Add MediaTek MT8192 clock provider device nodes chun-jie.chen
2021-03-31  8:38 ` chun-jie.chen
2021-03-31  8:38 ` [PATCH v2 1/2] arm64: dts: mediatek: Add mt8192 clock controllers chun-jie.chen
2021-03-31  8:38   ` chun-jie.chen
2021-03-31  8:38 ` chun-jie.chen [this message]
2021-03-31  8:38   ` [PATCH v2 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 chun-jie.chen

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