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From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com,
	robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org,
	leoyang.li@nxp.com, gustavo.pimentel@synopsys.com
Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com,
	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv5 4/6] dt-bindings: pci: layerscape-pci: Update the description of SCFG property
Date: Wed,  7 Apr 2021 11:09:46 +0800	[thread overview]
Message-ID: <20210407030948.3845-5-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20210407030948.3845-1-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
V5:
 - No change

 Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index d633c1fabdb4..8231f6729385 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -34,7 +34,7 @@ Required properties:
   "intr": The interrupt that is asserted for controller interrupts
 - fsl,pcie-scfg: Must include two entries.
   The first entry must be a link to the SCFG device node
-  The second entry must be '0' or '1' based on physical PCIe controller index.
+  The second entry is the physical PCIe controller index starting from '0'.
   This is used to get SCFG PEXN registers
 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
   of the data transferred from/to the IP block. This can avoid the software
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, lorenzo.pieralisi@arm.com,
	robh+dt@kernel.org, bhelgaas@google.com, shawnguo@kernel.org,
	leoyang.li@nxp.com, gustavo.pimentel@synopsys.com
Cc: minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com,
	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv5 4/6] dt-bindings: pci: layerscape-pci: Update the description of SCFG property
Date: Wed,  7 Apr 2021 11:09:46 +0800	[thread overview]
Message-ID: <20210407030948.3845-5-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <20210407030948.3845-1-Zhiqiang.Hou@nxp.com>

From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Update the description of the second entry of 'fsl,pcie-scfg' property,
as the LS1043A PCIe controller also has some control registers in SCFG
block, while it has 3 controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
V5:
 - No change

 Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index d633c1fabdb4..8231f6729385 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -34,7 +34,7 @@ Required properties:
   "intr": The interrupt that is asserted for controller interrupts
 - fsl,pcie-scfg: Must include two entries.
   The first entry must be a link to the SCFG device node
-  The second entry must be '0' or '1' based on physical PCIe controller index.
+  The second entry is the physical PCIe controller index starting from '0'.
   This is used to get SCFG PEXN registers
 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
   of the data transferred from/to the IP block. This can avoid the software
-- 
2.17.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-04-07  3:04 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-07  3:09 [PATCHv5 0/6] PCI: layerscape: Add power management support Zhiqiang Hou
2021-04-07  3:09 ` Zhiqiang Hou
2021-04-07  3:09 ` [PATCHv5 1/6] PCI: layerscape: Change to use the DWC common link-up check function Zhiqiang Hou
2021-04-07  3:09   ` Zhiqiang Hou
2021-04-07  3:09 ` [PATCHv5 2/6] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Zhiqiang Hou
2021-04-07  3:09   ` Zhiqiang Hou
2021-04-07  3:09 ` [PATCHv5 3/6] arm64: dts: layerscape: Add big-endian property for PCIe nodes Zhiqiang Hou
2021-04-07  3:09   ` Zhiqiang Hou
2021-04-07  3:09 ` Zhiqiang Hou [this message]
2021-04-07  3:09   ` [PATCHv5 4/6] dt-bindings: pci: layerscape-pci: Update the description of SCFG property Zhiqiang Hou
2021-04-07  3:09 ` [PATCHv5 5/6] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes Zhiqiang Hou
2021-04-07  3:09   ` Zhiqiang Hou
2021-04-07  3:09 ` [PATCHv5 6/6] PCI: layerscape: Add power management support Zhiqiang Hou
2021-04-07  3:09   ` Zhiqiang Hou
2021-04-09  0:08   ` Rob Herring
2021-04-09  0:08     ` Rob Herring
2021-11-12  0:37   ` Krzysztof Wilczyński
2021-11-12  0:37     ` Krzysztof Wilczyński
2021-11-18 12:29     ` Z.Q. Hou
2021-11-18 12:29       ` Z.Q. Hou
2021-11-11 21:21 ` [PATCHv5 0/6] " Li Yang
2021-11-11 21:21   ` Li Yang
2021-11-11 21:44   ` Bjorn Helgaas
2021-11-11 21:44     ` Bjorn Helgaas
2021-11-16 23:52     ` Leo Li
2021-11-16 23:52       ` Leo Li

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