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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 1/5] hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
Date: Mon, 12 Apr 2021 11:31:48 +0100	[thread overview]
Message-ID: <20210412103152.28433-2-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210412103152.28433-1-peter.maydell@linaro.org>

From: Zenghui Yu <yuzenghui@huawei.com>

The GSIV values in SMMUv3 IORT node are not correct as they don't match
the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
our emulated vSMMU.

Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210402084731.93-1-yuzenghui@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index f5a2b2d4cb5..60fe2e65a76 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -292,8 +292,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
         smmu->event_gsiv = cpu_to_le32(irq);
         smmu->pri_gsiv = cpu_to_le32(irq + 1);
-        smmu->gerr_gsiv = cpu_to_le32(irq + 2);
-        smmu->sync_gsiv = cpu_to_le32(irq + 3);
+        smmu->sync_gsiv = cpu_to_le32(irq + 2);
+        smmu->gerr_gsiv = cpu_to_le32(irq + 3);
 
         /* Identity RID mapping covering the whole input RID range */
         idmap = &smmu->id_mapping_array[0];
-- 
2.20.1



  reply	other threads:[~2021-04-12 10:33 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-12 10:31 [PULL 0/5] target-arm queue Peter Maydell
2021-04-12 10:31 ` Peter Maydell [this message]
2021-04-12 10:31 ` [PULL 2/5] hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs Peter Maydell
2021-04-12 10:31 ` [PULL 3/5] accel/tcg: Preserve PAGE_ANON when changing page permissions Peter Maydell
2021-04-12 10:31 ` [PULL 4/5] target/arm: Check PAGE_WRITE_ORG for MTE writeability Peter Maydell
2021-04-12 10:31 ` [PULL 5/5] exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 Peter Maydell
2021-04-12 10:42 ` [PULL 0/5] target-arm queue no-reply
2021-04-12 14:50 ` Peter Maydell

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