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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/8] drm/i915: Handle dbuf bypass path allocation earlier
Date: Fri, 16 Apr 2021 20:10:05 +0300	[thread overview]
Message-ID: <20210416171011.19012-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210416171011.19012-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We always reserve the same 4 dbuf blocks for the bypass path
allocation, so might as well do that when declaring the dbuf
size.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 8 ++++----
 drivers/gpu/drm/i915/intel_pm.c | 9 +--------
 2 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 484d2633894a..981d12702c49 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -647,7 +647,7 @@ static const struct intel_device_info chv_info = {
 	.has_gt_uc = 1, \
 	.display.has_hdcp = 1, \
 	.display.has_ipc = 1, \
-	.dbuf.size = 896, \
+	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
 	.dbuf.num_slices = 1
 
 #define SKL_PLATFORM \
@@ -720,14 +720,14 @@ static const struct intel_device_info skl_gt4_info = {
 static const struct intel_device_info bxt_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_BROXTON),
-	.dbuf.size = 512,
+	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ \
 };
 
 static const struct intel_device_info glk_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_GEMINILAKE),
 	.display.ver = 10,
-	.dbuf.size = 1024,
+	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
 	GLK_COLORS,
 };
 
@@ -790,7 +790,7 @@ static const struct intel_device_info cml_gt2_info = {
 #define GEN10_FEATURES \
 	GEN9_FEATURES, \
 	GEN(10), \
-	.dbuf.size = 1024, \
+	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
 	.display.has_dsc = 1, \
 	.has_coherent_ggtt = false, \
 	GLK_COLORS
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ced1eb32cb78..8d6ee5ad761e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4030,14 +4030,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 
 static int intel_dbuf_size(struct drm_i915_private *dev_priv)
 {
-	int ddb_size = INTEL_INFO(dev_priv)->dbuf.size;
-
-	drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
-
-	if (DISPLAY_VER(dev_priv) < 11)
-		return ddb_size - 4; /* 4 blocks for bypass path allocation */
-
-	return ddb_size;
+	return INTEL_INFO(dev_priv)->dbuf.size;
 }
 
 static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
-- 
2.26.3

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  parent reply	other threads:[~2021-04-16 17:10 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 1/8] drm/i915: Collect dbuf device info into a sub-struct Ville Syrjala
2021-04-16 17:10 ` Ville Syrjala [this message]
2021-04-16 17:10 ` [Intel-gfx] [PATCH 3/8] drm/i915: Store dbuf slice mask in device info Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 4/8] drm/i915: Use intel_dbuf_slice_size() Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 5/8] drm/i915: Use intel_de_rmw() for DBUF_POWER_REQUEST Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 6/8] drm/i915: Polish for_each_dbuf_slice() Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 7/8] drm/i915: Add enabledisable() Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 8/8] drm/i915: Say "enable foo" instead of "set foo to enabled" Ville Syrjala
2021-04-16 17:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: dbuf cleanups Patchwork
2021-04-16 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-04-16 17:30 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-04-16 17:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-16 19:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-04-20 12:57 ` [Intel-gfx] [PATCH 0/8] " Jani Nikula
2021-04-20 13:22   ` Ville Syrjälä

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