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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 7/8] drm/i915: Add enabledisable()
Date: Fri, 16 Apr 2021 20:10:10 +0300	[thread overview]
Message-ID: <20210416171011.19012-8-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210416171011.19012-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

'enable ? "enable" : "disable"' is a fairly common pattern in
out debug prints. Let's introduce a helper for it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c              | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_power.c    | 2 +-
 drivers/gpu/drm/i915/display/intel_dp.c               | 2 +-
 drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +-
 drivers/gpu/drm/i915/i915_utils.h                     | 5 +++++
 5 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4ef573883412..f4249f087fa7 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2334,8 +2334,8 @@ static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel
 	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
 			       enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
 		drm_dbg_kms(&i915->drm,
-			    "Failed to set MSA_TIMING_PAR_IGNORE %s in the sink\n",
-			    enable ? "enable" : "disable");
+			    "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
+			    enabledisable(enable));
 }
 
 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0fb4864a191a..d48dd15a4f6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4766,7 +4766,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
 	state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE;
 	drm_WARN(&dev_priv->drm, enable != state,
 		 "DBuf slice %d power %s timeout!\n",
-		 slice, enable ? "enable" : "disable");
+		 slice, enabledisable(enable));
 }
 
 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5ee953aaa00c..44109a4b69aa 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1861,7 +1861,7 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
 	if (ret < 0)
 		drm_dbg_kms(&i915->drm,
 			    "Failed to %s sink decompression state\n",
-			    enable ? "enable" : "disable");
+			    enabledisable(enable));
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 4f8337c7fd2e..8e9ac9ba1d38 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -291,7 +291,7 @@ static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
 	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
 			       reg_val) != 1) {
 		drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
-			    enable ? "enable" : "disable");
+			    enabledisable(enable));
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h
index abd4dcd9f79c..f02f52ab5070 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -418,6 +418,11 @@ static inline const char *onoff(bool v)
 	return v ? "on" : "off";
 }
 
+static inline const char *enabledisable(bool v)
+{
+	return v ? "enable" : "disable";
+}
+
 static inline const char *enableddisabled(bool v)
 {
 	return v ? "enabled" : "disabled";
-- 
2.26.3

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  parent reply	other threads:[~2021-04-16 17:10 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-16 17:10 [Intel-gfx] [PATCH 0/8] drm/i915: dbuf cleanups Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 1/8] drm/i915: Collect dbuf device info into a sub-struct Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 2/8] drm/i915: Handle dbuf bypass path allocation earlier Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 3/8] drm/i915: Store dbuf slice mask in device info Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 4/8] drm/i915: Use intel_dbuf_slice_size() Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 5/8] drm/i915: Use intel_de_rmw() for DBUF_POWER_REQUEST Ville Syrjala
2021-04-16 17:10 ` [Intel-gfx] [PATCH 6/8] drm/i915: Polish for_each_dbuf_slice() Ville Syrjala
2021-04-16 17:10 ` Ville Syrjala [this message]
2021-04-16 17:10 ` [Intel-gfx] [PATCH 8/8] drm/i915: Say "enable foo" instead of "set foo to enabled" Ville Syrjala
2021-04-16 17:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: dbuf cleanups Patchwork
2021-04-16 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-04-16 17:30 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-04-16 17:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-16 19:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-04-20 12:57 ` [Intel-gfx] [PATCH 0/8] " Jani Nikula
2021-04-20 13:22   ` Ville Syrjälä

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