[PATCH 1/5] misc: doc: Add binding doc for the afi config driver

[Nava kishore Manne <nava.manne@xilinx.com>]

This patch adds the binding document for the afi config
driver.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
---
 .../bindings/misc/xlnx,zynq-afi-fpga.yaml     | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml

diff --git a/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml b/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
new file mode 100644
index 000000000000..9c20a192d6a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,zynq-afi-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq AFI interface Manager.
+
+maintainers:
+  - Nava kishore Manne <nava.manne@xilinx.com>
+
+description: |
+  The Zynq Processing System core provides access from PL masters to PS
+  internal peripherals, and memory through AXI FIFO interface(AFI)
+  interfaces.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - xlnx,zynq-afi-fpga
+  reg:
+    maxItems: 1
+
+  xlnx,afi-buswidth:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: |
+            Size of the afi bus width.
+            0 - 64-bit AXI data width.
+            1 - 32-bit AXI data width.
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - xlnx,afi-buswidth
+
+additionalProperties: false
+
+examples:
+  - |
+    afi0: afi@f8008000 {
+        compatible = "xlnx,zynq-afi-fpga";
+        reg = <0xf8008000 0x1000>;
+        xlnx,afi-buswidth = <1>;
+    };
+...
-- 
2.18.0