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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>
Subject: [PATCH 2/5] target/mips: Simplify CP0 check in nanoMIPS P.LS.E0 EVA pool
Date: Tue, 20 Apr 2021 21:34:50 +0200	[thread overview]
Message-ID: <20210420193453.1913810-3-f4bug@amsat.org> (raw)
In-Reply-To: <20210420193453.1913810-1-f4bug@amsat.org>

The nanoMIPS P.LS.E0 pool contains the EVA instructions,
which are privileged. Simplify by moving the CP0 check
at the top of the pool swich case.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 16 +---------------
 1 file changed, 1 insertion(+), 15 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9acca6ef045..03fb67f6f22 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20906,27 +20906,24 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                 }
                 break;
             case NM_P_LS_E0:
+                check_cp0_enabled(ctx);
                 switch (extract32(ctx->opcode, 11, 4)) {
                 case NM_LBE:
                     check_eva(ctx);
-                    check_cp0_enabled(ctx);
                     gen_ld(ctx, OPC_LBE, rt, rs, s);
                     break;
                 case NM_SBE:
                     check_eva(ctx);
-                    check_cp0_enabled(ctx);
                     gen_st(ctx, OPC_SBE, rt, rs, s);
                     break;
                 case NM_LBUE:
                     check_eva(ctx);
-                    check_cp0_enabled(ctx);
                     gen_ld(ctx, OPC_LBUE, rt, rs, s);
                     break;
                 case NM_P_PREFE:
                     if (rt == 31) {
                         /* case NM_SYNCIE */
                         check_eva(ctx);
-                        check_cp0_enabled(ctx);
                         /*
                          * Break the TB to be able to sync copied instructions
                          * immediately.
@@ -20935,39 +20932,32 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     } else {
                         /* case NM_PREFE */
                         check_eva(ctx);
-                        check_cp0_enabled(ctx);
                         /* Treat as NOP. */
                     }
                     break;
                 case NM_LHE:
                     check_eva(ctx);
-                    check_cp0_enabled(ctx);
                     gen_ld(ctx, OPC_LHE, rt, rs, s);
                     break;
                 case NM_SHE:
                     check_eva(ctx);
-                    check_cp0_enabled(ctx);
                     gen_st(ctx, OPC_SHE, rt, rs, s);
                     break;
                 case NM_LHUE:
                     check_eva(ctx);
-                    check_cp0_enabled(ctx);
                     gen_ld(ctx, OPC_LHUE, rt, rs, s);
                     break;
                 case NM_CACHEE:
                     check_eva(ctx);
-                    check_cp0_enabled(ctx);
                     check_nms_dl_il_sl_tl_l2c(ctx);
                     gen_cache_operation(ctx, rt, rs, s);
                     break;
                 case NM_LWE:
                     check_eva(ctx);
-                    check_cp0_enabled(ctx);
                     gen_ld(ctx, OPC_LWE, rt, rs, s);
                     break;
                 case NM_SWE:
                     check_eva(ctx);
-                    check_cp0_enabled(ctx);
                     gen_st(ctx, OPC_SWE, rt, rs, s);
                     break;
                 case NM_P_LLE:
@@ -20975,13 +20965,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     case NM_LLE:
                         check_xnp(ctx);
                         check_eva(ctx);
-                        check_cp0_enabled(ctx);
                         gen_ld(ctx, OPC_LLE, rt, rs, s);
                         break;
                     case NM_LLWPE:
                         check_xnp(ctx);
                         check_eva(ctx);
-                        check_cp0_enabled(ctx);
                         gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
                         break;
                     default:
@@ -20994,13 +20982,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     case NM_SCE:
                         check_xnp(ctx);
                         check_eva(ctx);
-                        check_cp0_enabled(ctx);
                         gen_st_cond(ctx, rt, rs, s, MO_TESL, true);
                         break;
                     case NM_SCWPE:
                         check_xnp(ctx);
                         check_eva(ctx);
-                        check_cp0_enabled(ctx);
                         gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
                                  true);
                         break;
-- 
2.26.3



  parent reply	other threads:[~2021-04-20 19:39 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-20 19:34 [PATCH 0/5] target/mips: Make check_cp0_enabled() return a boolean Philippe Mathieu-Daudé
2021-04-20 19:34 ` [PATCH 1/5] target/mips: Remove duplicated check_cp0_enabled() calls in gen_cp0() Philippe Mathieu-Daudé
2021-04-21  1:31   ` Richard Henderson
2021-04-21  1:37   ` Richard Henderson
2021-04-20 19:34 ` Philippe Mathieu-Daudé [this message]
2021-04-21  1:35   ` [PATCH 2/5] target/mips: Simplify CP0 check in nanoMIPS P.LS.E0 EVA pool Richard Henderson
2021-04-20 19:34 ` [PATCH 3/5] target/mips: Make check_cp0_enabled() return a boolean Philippe Mathieu-Daudé
2021-04-21  1:35   ` Richard Henderson
2021-04-20 19:34 ` [PATCH 4/5] target/mips: Use check_cp0_enabled() returned value Philippe Mathieu-Daudé
2021-04-21  1:43   ` Richard Henderson
2021-04-20 19:34 ` [RFC PATCH 5/5] target/mips: Restrict EVA opcodes to system emulation Philippe Mathieu-Daudé
2021-04-21  1:40   ` Richard Henderson

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