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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>
Subject: [RFC PATCH 5/5] target/mips: Restrict EVA opcodes to system emulation
Date: Tue, 20 Apr 2021 21:34:53 +0200	[thread overview]
Message-ID: <20210420193453.1913810-6-f4bug@amsat.org> (raw)
In-Reply-To: <20210420193453.1913810-1-f4bug@amsat.org>

Enhanced Virtual Address (EVA) instructions are restricted
to Kernel execution mode, thus not available on user emulation.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
RFC because I'd rather not use such #ifdef'ry again.
TODO: have the compiler elide this code.

 target/mips/translate.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index dfa26569077..77115721a97 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -15245,8 +15245,11 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
     uint16_t insn;
     int rt, rs, rd, rr;
     int16_t imm;
-    uint32_t op, minor, minor2, mips32_op;
+    uint32_t op, minor, mips32_op;
     uint32_t cond, fmt, cc;
+#ifndef CONFIG_USER_ONLY
+    uint32_t minor2;
+#endif /* !CONFIG_USER_ONLY */
 
     insn = translator_lduw(env, ctx->base.pc_next + 2);
     ctx->opcode = (ctx->opcode << 16) | insn;
@@ -16205,6 +16208,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
             gen_st_cond(ctx, rt, rs, offset, MO_TEQ, false);
             break;
 #endif
+#ifndef CONFIG_USER_ONLY
         case LD_EVA:
             if (!ctx->eva) {
                 MIPS_INVAL("pool32c ld-eva");
@@ -16294,6 +16298,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
                 goto do_st_lr;
             };
             break;
+#endif /* !CONFIG_USER_ONLY */
         case PREF:
             /* Treat as no-op */
             if ((ctx->insn_flags & ISA_MIPS_R6) && (rt >= 24)) {
@@ -24486,16 +24491,18 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
 {
     int rs, rt, rd, sa;
     uint32_t op1, op2;
-    int16_t imm;
 
     rs = (ctx->opcode >> 21) & 0x1f;
     rt = (ctx->opcode >> 16) & 0x1f;
     rd = (ctx->opcode >> 11) & 0x1f;
     sa = (ctx->opcode >> 6) & 0x1f;
-    imm = sextract32(ctx->opcode, 7, 9);
 
     op1 = MASK_SPECIAL3(ctx->opcode);
 
+#ifndef CONFIG_USER_ONLY
+    int16_t imm;
+
+    imm = sextract32(ctx->opcode, 7, 9);
     /*
      * EVA loads and stores overlap Loongson 2E instructions decoded by
      * decode_opc_special3_legacy(), so be careful to allow their decoding when
@@ -24537,6 +24544,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
             return;
         }
     }
+#endif /* !CONFIG_USER_ONLY */
 
     switch (op1) {
     case OPC_EXT:
-- 
2.26.3



  parent reply	other threads:[~2021-04-20 19:41 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-20 19:34 [PATCH 0/5] target/mips: Make check_cp0_enabled() return a boolean Philippe Mathieu-Daudé
2021-04-20 19:34 ` [PATCH 1/5] target/mips: Remove duplicated check_cp0_enabled() calls in gen_cp0() Philippe Mathieu-Daudé
2021-04-21  1:31   ` Richard Henderson
2021-04-21  1:37   ` Richard Henderson
2021-04-20 19:34 ` [PATCH 2/5] target/mips: Simplify CP0 check in nanoMIPS P.LS.E0 EVA pool Philippe Mathieu-Daudé
2021-04-21  1:35   ` Richard Henderson
2021-04-20 19:34 ` [PATCH 3/5] target/mips: Make check_cp0_enabled() return a boolean Philippe Mathieu-Daudé
2021-04-21  1:35   ` Richard Henderson
2021-04-20 19:34 ` [PATCH 4/5] target/mips: Use check_cp0_enabled() returned value Philippe Mathieu-Daudé
2021-04-21  1:43   ` Richard Henderson
2021-04-20 19:34 ` Philippe Mathieu-Daudé [this message]
2021-04-21  1:40   ` [RFC PATCH 5/5] target/mips: Restrict EVA opcodes to system emulation Richard Henderson

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