From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>, Frank Chang <frank.chang@sifive.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Kito Cheng <kito.cheng@sifive.com> Subject: [PATCH v5 10/17] target/riscv: rvb: shift ones Date: Wed, 21 Apr 2021 12:13:52 +0800 [thread overview] Message-ID: <20210421041400.22243-11-frank.chang@sifive.com> (raw) In-Reply-To: <20210421041400.22243-1-frank.chang@sifive.com> From: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn32-64.decode | 4 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvb.c.inc | 48 +++++++++++++++++++++++++ target/riscv/translate.c | 14 ++++++++ 4 files changed, 70 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index f6c63c31b03..8c3ed33077e 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -98,7 +98,11 @@ bsetw 0010100 .......... 001 ..... 0111011 @r bclrw 0100100 .......... 001 ..... 0111011 @r binvw 0110100 .......... 001 ..... 0111011 @r bextw 0100100 .......... 101 ..... 0111011 @r +slow 0010000 .......... 001 ..... 0111011 @r +srow 0010000 .......... 101 ..... 0111011 @r bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 binviw 0110100 .......... 001 ..... 0011011 @sh5 +sloiw 0010000 .......... 001 ..... 0011011 @sh5 +sroiw 0010000 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 64d2b057764..0ea92312372 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -615,8 +615,12 @@ bset 0010100 .......... 001 ..... 0110011 @r bclr 0100100 .......... 001 ..... 0110011 @r binv 0110100 .......... 001 ..... 0110011 @r bext 0100100 .......... 101 ..... 0110011 @r +slo 0010000 .......... 001 ..... 0110011 @r +sro 0010000 .......... 101 ..... 0110011 @r bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh binvi 01101. ........... 001 ..... 0010011 @sh bexti 01001. ........... 101 ..... 0010011 @sh +sloi 00100. ........... 001 ..... 0010011 @sh +sroi 00100. ........... 101 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 0c41f135dc6..44f9f639240 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shifti(ctx, a, gen_bext); } +static bool trans_slo(DisasContext *ctx, arg_slo *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_slo); +} + +static bool trans_sloi(DisasContext *ctx, arg_sloi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_slo); +} + +static bool trans_sro(DisasContext *ctx, arg_sro *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_sro); +} + +static bool trans_sroi(DisasContext *ctx, arg_sroi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_sro); +} + /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -230,4 +254,28 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a) return gen_shiftw(ctx, a, gen_bext); } +static bool trans_slow(DisasContext *ctx, arg_slow *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_slo); +} + +static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_slo); +} + +static bool trans_srow(DisasContext *ctx, arg_srow *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_sro); +} + +static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_sro); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 28fb843a261..c7457553673 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -601,6 +601,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) tcg_gen_andi_tl(ret, ret, 1); } +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_not_tl(ret, arg1); + tcg_gen_shl_tl(ret, ret, arg2); + tcg_gen_not_tl(ret, ret); +} + +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_not_tl(ret, arg1); + tcg_gen_shr_tl(ret, ret, arg2); + tcg_gen_not_tl(ret, ret); +} + #ifdef TARGET_RISCV64 static void gen_ctzw(TCGv ret, TCGv arg1) -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Kito Cheng <kito.cheng@sifive.com>, Frank Chang <frank.chang@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Richard Henderson <richard.henderson@linaro.org> Subject: [PATCH v5 10/17] target/riscv: rvb: shift ones Date: Wed, 21 Apr 2021 12:13:52 +0800 [thread overview] Message-ID: <20210421041400.22243-11-frank.chang@sifive.com> (raw) In-Reply-To: <20210421041400.22243-1-frank.chang@sifive.com> From: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn32-64.decode | 4 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvb.c.inc | 48 +++++++++++++++++++++++++ target/riscv/translate.c | 14 ++++++++ 4 files changed, 70 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index f6c63c31b03..8c3ed33077e 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -98,7 +98,11 @@ bsetw 0010100 .......... 001 ..... 0111011 @r bclrw 0100100 .......... 001 ..... 0111011 @r binvw 0110100 .......... 001 ..... 0111011 @r bextw 0100100 .......... 101 ..... 0111011 @r +slow 0010000 .......... 001 ..... 0111011 @r +srow 0010000 .......... 101 ..... 0111011 @r bsetiw 0010100 .......... 001 ..... 0011011 @sh5 bclriw 0100100 .......... 001 ..... 0011011 @sh5 binviw 0110100 .......... 001 ..... 0011011 @sh5 +sloiw 0010000 .......... 001 ..... 0011011 @sh5 +sroiw 0010000 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 64d2b057764..0ea92312372 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -615,8 +615,12 @@ bset 0010100 .......... 001 ..... 0110011 @r bclr 0100100 .......... 001 ..... 0110011 @r binv 0110100 .......... 001 ..... 0110011 @r bext 0100100 .......... 101 ..... 0110011 @r +slo 0010000 .......... 001 ..... 0110011 @r +sro 0010000 .......... 101 ..... 0110011 @r bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh binvi 01101. ........... 001 ..... 0010011 @sh bexti 01001. ........... 101 ..... 0010011 @sh +sloi 00100. ........... 001 ..... 0010011 @sh +sroi 00100. ........... 101 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 0c41f135dc6..44f9f639240 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shifti(ctx, a, gen_bext); } +static bool trans_slo(DisasContext *ctx, arg_slo *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_slo); +} + +static bool trans_sloi(DisasContext *ctx, arg_sloi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_slo); +} + +static bool trans_sro(DisasContext *ctx, arg_sro *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_sro); +} + +static bool trans_sroi(DisasContext *ctx, arg_sroi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_sro); +} + /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -230,4 +254,28 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a) return gen_shiftw(ctx, a, gen_bext); } +static bool trans_slow(DisasContext *ctx, arg_slow *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_slo); +} + +static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_slo); +} + +static bool trans_srow(DisasContext *ctx, arg_srow *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_sro); +} + +static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_sro); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 28fb843a261..c7457553673 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -601,6 +601,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) tcg_gen_andi_tl(ret, ret, 1); } +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_not_tl(ret, arg1); + tcg_gen_shl_tl(ret, ret, arg2); + tcg_gen_not_tl(ret, ret); +} + +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_not_tl(ret, arg1); + tcg_gen_shr_tl(ret, ret, arg2); + tcg_gen_not_tl(ret, ret); +} + #ifdef TARGET_RISCV64 static void gen_ctzw(TCGv ret, TCGv arg1) -- 2.17.1
next prev parent reply other threads:[~2021-04-21 4:23 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-21 4:13 [PATCH v5 00/17] support subsets of bitmanip extension frank.chang 2021-04-21 4:13 ` [PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-21 4:13 ` [PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-27 6:01 ` Alistair Francis 2021-04-27 6:01 ` Alistair Francis 2021-04-27 7:13 ` Frank Chang 2021-04-27 7:13 ` Frank Chang 2021-04-21 4:13 ` [PATCH v5 03/17] target/riscv: rvb: count bits set frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-27 6:03 ` Alistair Francis 2021-04-27 6:03 ` Alistair Francis 2021-04-21 4:13 ` [PATCH v5 04/17] target/riscv: rvb: logic-with-negate frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-27 6:04 ` Alistair Francis 2021-04-27 6:04 ` Alistair Francis 2021-04-21 4:13 ` [PATCH v5 05/17] target/riscv: rvb: pack two words into one register frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-27 6:05 ` Alistair Francis 2021-04-27 6:05 ` Alistair Francis 2021-04-21 4:13 ` [PATCH v5 06/17] target/riscv: rvb: min/max instructions frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-27 6:06 ` Alistair Francis 2021-04-27 6:06 ` Alistair Francis 2021-04-21 4:13 ` [PATCH v5 07/17] target/riscv: rvb: sign-extend instructions frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-27 6:06 ` Alistair Francis 2021-04-27 6:06 ` Alistair Francis 2021-04-21 4:13 ` [PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-21 4:13 ` [PATCH v5 09/17] target/riscv: rvb: single-bit instructions frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-21 4:13 ` frank.chang [this message] 2021-04-21 4:13 ` [PATCH v5 10/17] target/riscv: rvb: shift ones frank.chang 2021-04-21 4:13 ` [PATCH v5 11/17] target/riscv: rvb: rotate (left/right) frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-21 4:13 ` [PATCH v5 12/17] target/riscv: rvb: generalized reverse frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-21 4:13 ` [PATCH v5 13/17] target/riscv: rvb: generalized or-combine frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-21 4:13 ` [PATCH v5 14/17] target/riscv: rvb: address calculation frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-21 4:13 ` [PATCH v5 15/17] target/riscv: rvb: add/shift with prefix zero-extend frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-21 4:13 ` [PATCH v5 16/17] target/riscv: rvb: support and turn on B-extension from command line frank.chang 2021-04-21 4:13 ` frank.chang 2021-04-21 4:13 ` [PATCH v5 17/17] target/riscv: rvb: add b-ext version cpu option frank.chang 2021-04-21 4:13 ` frank.chang
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210421041400.22243-11-frank.chang@sifive.com \ --to=frank.chang@sifive.com \ --cc=Alistair.Francis@wdc.com \ --cc=kbastian@mail.uni-paderborn.de \ --cc=kito.cheng@sifive.com \ --cc=palmer@dabbelt.com \ --cc=qemu-devel@nongnu.org \ --cc=qemu-riscv@nongnu.org \ --cc=richard.henderson@linaro.org \ --cc=sagark@eecs.berkeley.edu \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.