From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 13/17] drm/i915: Deduplicate icl DP HBR2 vs. eDP HBR3 table
Date: Wed, 21 Apr 2021 19:48:45 +0300 [thread overview]
Message-ID: <20210421164849.12806-14-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210421164849.12806-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The icl combo phy DP HBR2 is identical to the eDP HBR3 table.
Get rid of one redundant copy.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_ddi_buf_trans.c | 39 +++++--------------
1 file changed, 10 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 25702f40b3ce..0facbf556634 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -597,7 +597,7 @@ static const struct intel_ddi_buf_trans cnl_ddi_translations_edp_1_05V = {
};
/* icl_combo_phy_ddi_translations */
-static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2[] = {
+static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3[] = {
/* NT mV Trans mV db */
{ .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
{ .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
@@ -611,9 +611,9 @@ static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_dp_
{ .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
};
-static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2 = {
- .entries = _icl_combo_phy_ddi_translations_dp_hbr2,
- .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2),
+static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3 = {
+ .entries = _icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
+ .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3),
};
static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr2[] = {
@@ -635,25 +635,6 @@ static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2
.num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr2),
};
-static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_edp_hbr3[] = {
- /* NT mV Trans mV db */
- { .cnl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
- { .cnl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
- { .cnl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
- { .cnl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
- { .cnl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
- { .cnl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
- { .cnl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
- { .cnl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
- { .cnl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
- { .cnl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
-};
-
-static const struct intel_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3 = {
- .entries = _icl_combo_phy_ddi_translations_edp_hbr3,
- .num_entries = ARRAY_SIZE(_icl_combo_phy_ddi_translations_edp_hbr3),
-};
-
static const union intel_ddi_buf_trans_entry _icl_combo_phy_ddi_translations_hdmi[] = {
/* NT mV Trans mV db */
{ .cnl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */
@@ -1269,7 +1250,7 @@ icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2,
+ return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
n_entries);
}
@@ -1281,7 +1262,7 @@ icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (crtc_state->port_clock > 540000) {
- return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3,
+ return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
n_entries);
} else if (dev_priv->vbt.edp.low_vswing) {
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
@@ -1398,7 +1379,7 @@ jsl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2,
+ return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
n_entries);
}
@@ -1474,7 +1455,7 @@ tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (crtc_state->port_clock > 540000) {
- return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3,
+ return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
n_entries);
} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
@@ -1521,7 +1502,7 @@ dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
if (crtc_state->port_clock > 540000)
- return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3,
+ return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
n_entries);
else if (dev_priv->vbt.edp.low_vswing)
return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr2,
@@ -1563,7 +1544,7 @@ rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
if (crtc_state->port_clock > 540000) {
- return intel_get_buf_trans(&icl_combo_phy_ddi_translations_edp_hbr3,
+ return intel_get_buf_trans(&icl_combo_phy_ddi_translations_dp_hbr2_edp_hbr3,
n_entries);
} else if (dev_priv->vbt.edp.hobl && !intel_dp->hobl_failed) {
return intel_get_buf_trans(&tgl_combo_phy_ddi_translations_edp_hbr2_hobl,
--
2.26.3
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next prev parent reply other threads:[~2021-04-21 16:49 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-21 16:48 [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 01/17] drm/i915: s/intel/hsw/ for hsw/bde/skl buf trans Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 02/17] drm/i915: Introduce hsw_get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 03/17] drm/i915: Wrap the platform specific buf trans structs into a union Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 04/17] drm/i915: Rename dkl phy buf trans tables Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 05/17] drm/i915: Wrap the buf trans tables into a struct Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 06/17] drm/i915: Introduce intel_get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 07/17] drm/i915; Return the whole buf_trans struct from get_buf_trans() Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 08/17] drm/i915: Store the HDMI default entry in the bug trans struct Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 09/17] drm/i915: Introduce encoder->get_buf_trans() Ville Syrjala
2021-05-11 18:31 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 10/17] drm/i915: Clean up hsw/bdw/skl/kbl buf trans funcs Ville Syrjala
2021-05-12 18:53 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 11/17] drm/i915: Introduce rkl_get_combo_buf_trans() Ville Syrjala
2021-05-12 18:58 ` Jani Nikula
2021-04-21 16:48 ` [Intel-gfx] [PATCH 12/17] drm/i915: Fix dg1 buf trans tables Ville Syrjala
2021-05-04 10:15 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-05-12 19:05 ` Jani Nikula
2021-04-21 16:48 ` Ville Syrjala [this message]
2021-04-21 16:48 ` [Intel-gfx] [PATCH 14/17] drm/i915: Fix ehl edp hbr2 vswing table Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 15/17] drm/i915: Clean up jsl/ehl buf trans functions Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 16/17] drm/i915: Nuke buf_trans hdmi functions Ville Syrjala
2021-04-21 16:48 ` [Intel-gfx] [PATCH 17/17] drm/i915: Add the missing adls vswing tables Ville Syrjala
2021-04-22 6:20 ` kernel test robot
2021-04-22 6:20 ` kernel test robot
2021-05-04 10:16 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-04-21 17:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes Patchwork
2021-04-21 17:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-04-21 17:22 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-04-21 17:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-22 1:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-04 12:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork
2021-05-04 12:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-04 12:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-04 14:05 ` [Intel-gfx] [PATCH 00/17] drm/i915: DDI buf trans cleaup and fixes Jani Nikula
2021-05-04 14:18 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: DDI buf trans cleaup and fixes (rev3) Patchwork
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