From: "Philippe Mathieu-Daudé" <f4bug@amsat.org> To: qemu-devel@nongnu.org Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>, 1926277@bugs.launchpad.net, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, "Edgar E . Iglesias" <edgar.iglesias@gmail.com>, "Aurelien Jarno" <aurelien@aurel32.net> Subject: [PATCH v2] target/mips: Only update MVPControl.EVP bit if executed by master VPE Date: Tue, 27 Apr 2021 15:33:37 +0200 [thread overview] Message-ID: <20210427133343.159718-1-f4bug@amsat.org> (raw) According to the 'MIPS MT Application-Specific Extension' manual: If the VPE executing the instruction is not a Master VPE, with the MVP bit of the VPEConf0 register set, the EVP bit is unchanged by the instruction. Modify the DVPE/EVPE opcodes to only update the MVPControl.EVP bit if executed on a master VPE. Reported-by: Hansni Bu <https://launchpad.net/%7Ehansni/+contactuser> Buglink: https://bugs.launchpad.net/qemu/+bug/1926277 Fixes: f249412c749 ("mips: Add MT halting and waking of VPEs") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- Supersedes: <20210427103555.112652-1-f4bug@amsat.org> v2: Check VPEConf0.MVP bit (hansni) --- target/mips/cp0_helper.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index aae2af6eccc..d5f274f5cdf 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -1635,12 +1635,14 @@ target_ulong helper_dvpe(CPUMIPSState *env) CPUState *other_cs = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu = MIPS_CPU(other_cs); - /* Turn off all VPEs except the one executing the dvpe. */ - if (&other_cpu->env != env) { - other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); - mips_vpe_sleep(other_cpu); + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu = MIPS_CPU(other_cs); + /* Turn off all VPEs except the one executing the dvpe. */ + if (&other_cpu->env != env) { + other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); + mips_vpe_sleep(other_cpu); + } } } return prev; @@ -1651,15 +1653,17 @@ target_ulong helper_evpe(CPUMIPSState *env) CPUState *other_cs = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu = MIPS_CPU(other_cs); + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu = MIPS_CPU(other_cs); - if (&other_cpu->env != env - /* If the VPE is WFI, don't disturb its sleep. */ - && !mips_vpe_is_wfi(other_cpu)) { - /* Enable the VPE. */ - other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); - mips_vpe_wake(other_cpu); /* And wake it up. */ + if (&other_cpu->env != env + /* If the VPE is WFI, don't disturb its sleep. */ + && !mips_vpe_is_wfi(other_cpu)) { + /* Enable the VPE. */ + other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); + mips_vpe_wake(other_cpu); /* And wake it up. */ + } } } return prev; -- 2.26.3
WARNING: multiple messages have this Message-ID (diff)
From: "Philippe Mathieu-Daudé" <1926277@bugs.launchpad.net> To: qemu-devel@nongnu.org Subject: [Bug 1926277] [PATCH v2] target/mips: Only update MVPControl.EVP bit if executed by master VPE Date: Tue, 27 Apr 2021 13:33:37 -0000 [thread overview] Message-ID: <20210427133343.159718-1-f4bug@amsat.org> (raw) Message-ID: <20210427133337.d7JBProvwDCa-CtnZuam7kmaJnPHuBjUhyqdwMsgL0s@z> (raw) In-Reply-To: 161951518027.9817.15696784713381088226.malonedeb@soybean.canonical.com According to the 'MIPS MT Application-Specific Extension' manual: If the VPE executing the instruction is not a Master VPE, with the MVP bit of the VPEConf0 register set, the EVP bit is unchanged by the instruction. Modify the DVPE/EVPE opcodes to only update the MVPControl.EVP bit if executed on a master VPE. Reported-by: Hansni Bu <https://launchpad.net/%7Ehansni/+contactuser> Buglink: https://bugs.launchpad.net/qemu/+bug/1926277 Fixes: f249412c749 ("mips: Add MT halting and waking of VPEs") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- Supersedes: <20210427103555.112652-1-f4bug@amsat.org> v2: Check VPEConf0.MVP bit (hansni) --- target/mips/cp0_helper.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index aae2af6eccc..d5f274f5cdf 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -1635,12 +1635,14 @@ target_ulong helper_dvpe(CPUMIPSState *env) CPUState *other_cs = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu = MIPS_CPU(other_cs); - /* Turn off all VPEs except the one executing the dvpe. */ - if (&other_cpu->env != env) { - other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); - mips_vpe_sleep(other_cpu); + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu = MIPS_CPU(other_cs); + /* Turn off all VPEs except the one executing the dvpe. */ + if (&other_cpu->env != env) { + other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); + mips_vpe_sleep(other_cpu); + } } } return prev; @@ -1651,15 +1653,17 @@ target_ulong helper_evpe(CPUMIPSState *env) CPUState *other_cs = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu = MIPS_CPU(other_cs); + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu = MIPS_CPU(other_cs); - if (&other_cpu->env != env - /* If the VPE is WFI, don't disturb its sleep. */ - && !mips_vpe_is_wfi(other_cpu)) { - /* Enable the VPE. */ - other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); - mips_vpe_wake(other_cpu); /* And wake it up. */ + if (&other_cpu->env != env + /* If the VPE is WFI, don't disturb its sleep. */ + && !mips_vpe_is_wfi(other_cpu)) { + /* Enable the VPE. */ + other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); + mips_vpe_wake(other_cpu); /* And wake it up. */ + } } } return prev; -- 2.26.3 -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1926277 Title: MIPS MT dvpe does not regard VPEConf0.MVP Status in QEMU: Confirmed Bug description: Hi, According to MIPS32® Architecture for Programmers VolumeIV-f: The MIPS® MT Application-Specific Extension to the MIPS32® Architecture, for instruction: dvpe, evpe: If the VPE executing the instruction is not a Master VPE, with the MVP bit of the VPEConf0 register set, the EVP bit is unchanged by the instruction. The pseudo code is: data ← MVPControl GPR[rt] ← data if(VPEConf0.MVP = 1) then MVPControl.EVP ← sc endif However the helper functions of dvpe, evpe does not regard the VPEConf0.MVP bit, namely, it does not check if the VPE is a master VPE. Code is copied below as: target_ulong helper_dvpe(CPUMIPSState *env) { CPUState *other_cs = first_cpu; target_ulong prev = env->mvp->CP0_MVPControl; CPU_FOREACH(other_cs) { MIPSCPU *other_cpu = MIPS_CPU(other_cs); /* Turn off all VPEs except the one executing the dvpe. */ if (&other_cpu->env != env) { other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); mips_vpe_sleep(other_cpu); } } return prev; } Is this a bug? QEMU head commit: 0cef06d18762374c94eb4d511717a4735d668a24 is checked. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1926277/+subscriptions
next reply other threads:[~2021-04-27 13:35 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-27 13:33 Philippe Mathieu-Daudé [this message] 2021-04-27 13:33 ` [Bug 1926277] [PATCH v2] target/mips: Only update MVPControl.EVP bit if executed by master VPE Philippe Mathieu-Daudé -- strict thread matches above, loose matches on Subject: below -- 2021-04-27 10:35 [PATCH] target/mips: Only update MVPControl.EVP bit if executed on a " Philippe Mathieu-Daudé 2021-04-27 10:35 ` [Bug 1926277] Re: MIPS MT dvpe does not regard VPEConf0.MVP Philippe Mathieu-Daudé 2021-04-27 9:19 [Bug 1926277] [NEW] " Hansni Bu 2021-04-27 11:42 ` [Bug 1926277] " Hansni Bu 2021-04-27 13:29 ` Philippe Mathieu-Daudé 2021-05-09 16:16 ` Philippe Mathieu-Daudé
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