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From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org,
	sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
	richard.henderson@linaro.org, qemu-devel@nongnu.org,
	space.monkey.delivers@gmail.com,
	Alistair Francis <alistair.francis@wdc.com>,
	kupokupokupopo@gmail.com, palmer@dabbelt.com
Subject: [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
Date: Wed, 28 Apr 2021 01:06:15 +0300	[thread overview]
Message-ID: <20210427220615.12763-7-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20210427220615.12763-1-space.monkey.delivers@gmail.com>

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0682410f5d..fecc64d7ba 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -502,6 +502,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 #ifndef CONFIG_USER_ONLY
             env->mmte |= PM_EXT_INITIAL;
 #endif
+            target_misa |= RVJ;
         }
         if (cpu->cfg.ext_v) {
             target_misa |= RVV;
@@ -574,6 +575,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+    DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-- 
2.20.1



WARNING: multiple messages have this Message-ID (diff)
From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org,
	space.monkey.delivers@gmail.com, kupokupokupopo@gmail.com,
	palmer@dabbelt.com, Alistair.Francis@wdc.com,
	sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on
Date: Wed, 28 Apr 2021 01:06:15 +0300	[thread overview]
Message-ID: <20210427220615.12763-7-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20210427220615.12763-1-space.monkey.delivers@gmail.com>

Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0682410f5d..fecc64d7ba 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -502,6 +502,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 #ifndef CONFIG_USER_ONLY
             env->mmte |= PM_EXT_INITIAL;
 #endif
+            target_misa |= RVJ;
         }
         if (cpu->cfg.ext_v) {
             target_misa |= RVV;
@@ -574,6 +575,7 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+    DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-- 
2.20.1



  parent reply	other threads:[~2021-04-27 22:11 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-27 22:06 [PATCH v8 0/6] RISC-V Pointer Masking implementation Alexey Baturo
2021-04-27 22:06 ` Alexey Baturo
2021-04-27 22:06 ` [PATCH v8 1/6] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2021-04-27 22:06   ` Alexey Baturo
2021-04-27 22:06 ` [PATCH v8 2/6] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo
2021-04-27 22:06   ` Alexey Baturo
2021-04-27 22:06 ` [PATCH v8 3/6] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2021-04-27 22:06   ` Alexey Baturo
2021-04-27 22:06 ` [PATCH v8 4/6] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2021-04-27 22:06   ` Alexey Baturo
2021-04-27 22:06 ` [PATCH v8 5/6] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2021-04-27 22:06   ` Alexey Baturo
2021-04-27 22:06 ` Alexey Baturo [this message]
2021-04-27 22:06   ` [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo
2021-04-27 22:18 ` [PATCH v8 0/6] RISC-V Pointer Masking implementation no-reply
2021-04-28  4:18 [PATCH RESEND " Alexey Baturo
2021-04-28  4:18 ` [PATCH v8 6/6] [RISCV_PM] Allow experimental J-ext to be turned on Alexey Baturo
2021-04-28  4:18   ` Alexey Baturo

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