From: Jerome Brunet <jbrunet@baylibre.com> To: Neil Armstrong <narmstrong@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com>, Kevin Hilman <khilman@baylibre.com>, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: meson: g12a: fix gp0 and hifi ranges Date: Thu, 29 Apr 2021 11:03:25 +0200 [thread overview] Message-ID: <20210429090325.60970-1-jbrunet@baylibre.com> (raw) While some SoC samples are able to lock with a PLL factor of 55, others samples can't. ATM, a minimum of 60 appears to work on all the samples I have tried. Even with 60, it sometimes takes a long time for the PLL to eventually lock. The documentation says that the minimum rate of these PLLs DCO should be 3GHz, a factor of 125. Let's use that to be on the safe side. With factor range changed, the PLL seems to lock quickly (enough) so far. It is still unclear if the range was the only reason for the delay. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/clk/meson/g12a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index b080359b4645..a805bac93c11 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -1603,7 +1603,7 @@ static struct clk_regmap g12b_cpub_clk_trace = { }; static const struct pll_mult_range g12a_gp0_pll_mult_range = { - .min = 55, + .min = 125, .max = 255, }; -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com> To: Neil Armstrong <narmstrong@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com>, Kevin Hilman <khilman@baylibre.com>, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] clk: meson: g12a: fix gp0 and hifi ranges Date: Thu, 29 Apr 2021 11:03:25 +0200 [thread overview] Message-ID: <20210429090325.60970-1-jbrunet@baylibre.com> (raw) While some SoC samples are able to lock with a PLL factor of 55, others samples can't. ATM, a minimum of 60 appears to work on all the samples I have tried. Even with 60, it sometimes takes a long time for the PLL to eventually lock. The documentation says that the minimum rate of these PLLs DCO should be 3GHz, a factor of 125. Let's use that to be on the safe side. With factor range changed, the PLL seems to lock quickly (enough) so far. It is still unclear if the range was the only reason for the delay. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/clk/meson/g12a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index b080359b4645..a805bac93c11 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -1603,7 +1603,7 @@ static struct clk_regmap g12b_cpub_clk_trace = { }; static const struct pll_mult_range g12a_gp0_pll_mult_range = { - .min = 55, + .min = 125, .max = 255, }; -- 2.31.1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic
next reply other threads:[~2021-04-29 9:03 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-29 9:03 Jerome Brunet [this message] 2021-04-29 9:03 ` [PATCH] clk: meson: g12a: fix gp0 and hifi ranges Jerome Brunet 2021-04-29 9:20 ` Neil Armstrong 2021-04-29 9:20 ` Neil Armstrong 2021-04-29 9:45 ` Jerome Brunet 2021-04-29 9:45 ` Jerome Brunet 2021-04-29 12:15 ` Neil Armstrong 2021-04-29 12:15 ` Neil Armstrong 2021-04-29 12:16 ` Jerome Brunet 2021-04-29 12:16 ` Jerome Brunet 2021-05-20 14:02 ` Neil Armstrong 2021-05-20 14:02 ` Neil Armstrong 2021-05-24 9:38 ` Jerome Brunet 2021-05-24 9:38 ` Jerome Brunet -- strict thread matches above, loose matches on Subject: below -- 2019-03-25 10:42 Jerome Brunet 2019-03-25 10:42 ` Jerome Brunet 2019-03-25 12:18 ` Neil Armstrong 2019-03-25 12:18 ` Neil Armstrong 2019-03-29 8:39 ` Neil Armstrong 2019-03-29 8:39 ` Neil Armstrong
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