[Intel-gfx] [PATCH] drm/i915/display/tgl+: Add new sequence step for MST + FEC

["José Roberto de Souza" <jose.souza@intel.com>]

For DP 1.4 sinks + MST + FEC it is required to prevent a FEC stall
signaling.

BSpec: 49190
BSpec: 54128
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 28 +++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h             |  1 +
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 9e406d9722c5..e7b636ba6982 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -376,6 +376,30 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state,
 					  old_crtc_state, old_conn_state);
 }
 
+static void intel_mst_config_fec(struct intel_encoder *encoder,
+				 const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+	if (DISPLAY_VER(i915) >= 12 && crtc_state->fec_enable &&
+	    intel_dp->dpcd[DP_DPCD_REV] == DP_DPCD_REV_14)
+		intel_de_rmw(i915, CHICKEN_TRANS(crtc_state->cpu_transcoder),
+			     0, PREVENT_FEC_STALL_SIGNALING);
+}
+
+static void intel_mst_unconfig_fec(struct intel_encoder *encoder,
+				   const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+	if (DISPLAY_VER(i915) >= 12 && crtc_state->fec_enable &&
+	    intel_dp->dpcd[DP_DPCD_REV] == DP_DPCD_REV_14)
+		intel_de_rmw(i915, CHICKEN_TRANS(crtc_state->cpu_transcoder),
+			     PREVENT_FEC_STALL_SIGNALING, 0);
+}
+
 static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 				      struct intel_encoder *encoder,
 				      const struct intel_crtc_state *old_crtc_state,
@@ -400,6 +424,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 
 	intel_disable_pipe(old_crtc_state);
 
+	intel_mst_unconfig_fec(encoder, old_crtc_state);
+
 	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
 
 	clear_act_sent(encoder, old_crtc_state);
@@ -563,6 +589,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
 
 	drm_dp_update_payload_part2(&intel_dp->mst_mgr);
 
+	intel_mst_config_fec(encoder, pipe_config);
+
 	intel_enable_pipe(pipe_config);
 
 	intel_crtc_vblank_on(pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ffd173f8b7f..6fe7aebed4f9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8086,6 +8086,7 @@ enum {
 #define  HSW_FRAME_START_DELAY_MASK	(3 << 27)
 #define  HSW_FRAME_START_DELAY(x)	((x) << 27) /* 0-3 */
 #define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1 << 25) /* GLK and CNL+ */
+#define  PREVENT_FEC_STALL_SIGNALING	BIT(23)
 #define  DDI_TRAINING_OVERRIDE_ENABLE	(1 << 19)
 #define  DDI_TRAINING_OVERRIDE_VALUE	(1 << 18)
 #define  DDIE_TRAINING_OVERRIDE_ENABLE	(1 << 17) /* CHICKEN_TRANS_A only */
-- 
2.31.1

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