From: chun-jie.chen <chun-jie.chen@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Nicolas Boichat <drinkcat@chromium.org>, "Rob Herring" <robh+dt@kernel.org> Cc: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <srv_heupstream@mediatek.com>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, chun-jie.chen <chun-jie.chen@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com> Subject: [PATCH v8 07/22] clk: mediatek: Fix asymmetrical PLL enable and disable control Date: Wed, 5 May 2021 18:06:59 +0800 [thread overview] Message-ID: <20210505100714.3582-8-chun-jie.chen@mediatek.com> (raw) In-Reply-To: <20210505100714.3582-1-chun-jie.chen@mediatek.com> In fact, the en_mask is a combination of divider enable mask and pll enable bit(bit0). Before this patch, we enabled both divider mask and bit0 in prepare(), but only cleared the bit0 in unprepare(). In the future, we hope en_mask will only be used as divider enable mask. The enable register(CON0) will be set in 2 steps: first is divider mask, and then bit0 during prepare(), and vice versa. But considering backward compatibility, at this stage we allow en_mask to be a combination or a pure divider enable mask. And then we will make en_mask a pure divider enable mask in another following patch series. Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com> --- drivers/clk/mediatek/clk-pll.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index f440f2cd0b69..11ed5d1d1c36 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -238,6 +238,7 @@ static int mtk_pll_prepare(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); u32 r; + u32 div_en_mask; r = readl(pll->pwr_addr) | CON0_PWR_ON; writel(r, pll->pwr_addr); @@ -247,10 +248,15 @@ static int mtk_pll_prepare(struct clk_hw *hw) writel(r, pll->pwr_addr); udelay(1); - r = readl(pll->base_addr + REG_CON0); - r |= pll->data->en_mask; + r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN; writel(r, pll->base_addr + REG_CON0); + div_en_mask = pll->data->en_mask & ~CON0_BASE_EN; + if (div_en_mask) { + r = readl(pll->base_addr + REG_CON0) | div_en_mask; + writel(r, pll->base_addr + REG_CON0); + } + __mtk_pll_tuner_enable(pll); udelay(20); @@ -268,6 +274,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); u32 r; + u32 div_en_mask; if (pll->data->flags & HAVE_RST_BAR) { r = readl(pll->base_addr + REG_CON0); @@ -277,8 +284,13 @@ static void mtk_pll_unprepare(struct clk_hw *hw) __mtk_pll_tuner_disable(pll); - r = readl(pll->base_addr + REG_CON0); - r &= ~CON0_BASE_EN; + div_en_mask = pll->data->en_mask & ~CON0_BASE_EN; + if (div_en_mask) { + r = readl(pll->base_addr + REG_CON0) & ~div_en_mask; + writel(r, pll->base_addr + REG_CON0); + } + + r = readl(pll->base_addr + REG_CON0) & ~CON0_BASE_EN; writel(r, pll->base_addr + REG_CON0); r = readl(pll->pwr_addr) | CON0_ISO_EN; -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: chun-jie.chen <chun-jie.chen@mediatek.com> To: Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>, Nicolas Boichat <drinkcat@chromium.org>, "Rob Herring" <robh+dt@kernel.org> Cc: <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>, <srv_heupstream@mediatek.com>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, chun-jie.chen <chun-jie.chen@mediatek.com>, Weiyi Lu <weiyi.lu@mediatek.com> Subject: [PATCH v8 07/22] clk: mediatek: Fix asymmetrical PLL enable and disable control Date: Wed, 5 May 2021 18:06:59 +0800 [thread overview] Message-ID: <20210505100714.3582-8-chun-jie.chen@mediatek.com> (raw) In-Reply-To: <20210505100714.3582-1-chun-jie.chen@mediatek.com> In fact, the en_mask is a combination of divider enable mask and pll enable bit(bit0). Before this patch, we enabled both divider mask and bit0 in prepare(), but only cleared the bit0 in unprepare(). In the future, we hope en_mask will only be used as divider enable mask. The enable register(CON0) will be set in 2 steps: first is divider mask, and then bit0 during prepare(), and vice versa. But considering backward compatibility, at this stage we allow en_mask to be a combination or a pure divider enable mask. And then we will make en_mask a pure divider enable mask in another following patch series. Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: chun-jie.chen <chun-jie.chen@mediatek.com> --- drivers/clk/mediatek/clk-pll.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index f440f2cd0b69..11ed5d1d1c36 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -238,6 +238,7 @@ static int mtk_pll_prepare(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); u32 r; + u32 div_en_mask; r = readl(pll->pwr_addr) | CON0_PWR_ON; writel(r, pll->pwr_addr); @@ -247,10 +248,15 @@ static int mtk_pll_prepare(struct clk_hw *hw) writel(r, pll->pwr_addr); udelay(1); - r = readl(pll->base_addr + REG_CON0); - r |= pll->data->en_mask; + r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN; writel(r, pll->base_addr + REG_CON0); + div_en_mask = pll->data->en_mask & ~CON0_BASE_EN; + if (div_en_mask) { + r = readl(pll->base_addr + REG_CON0) | div_en_mask; + writel(r, pll->base_addr + REG_CON0); + } + __mtk_pll_tuner_enable(pll); udelay(20); @@ -268,6 +274,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); u32 r; + u32 div_en_mask; if (pll->data->flags & HAVE_RST_BAR) { r = readl(pll->base_addr + REG_CON0); @@ -277,8 +284,13 @@ static void mtk_pll_unprepare(struct clk_hw *hw) __mtk_pll_tuner_disable(pll); - r = readl(pll->base_addr + REG_CON0); - r &= ~CON0_BASE_EN; + div_en_mask = pll->data->en_mask & ~CON0_BASE_EN; + if (div_en_mask) { + r = readl(pll->base_addr + REG_CON0) & ~div_en_mask; + writel(r, pll->base_addr + REG_CON0); + } + + r = readl(pll->base_addr + REG_CON0) & ~CON0_BASE_EN; writel(r, pll->base_addr + REG_CON0); r = readl(pll->pwr_addr) | CON0_ISO_EN; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-05-05 10:14 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-05 10:06 [PATCH v8 00/22] Mediatek MT8192 clock support chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 02/22] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 03/22] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 04/22] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 05/22] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` [PATCH v8 06/22] clk: mediatek: Add dt-bindings of MT8192 clocks chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen 2021-05-05 10:06 ` chun-jie.chen [this message] 2021-05-05 10:06 ` [PATCH v8 07/22] clk: mediatek: Fix asymmetrical PLL enable and disable control chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 08/22] clk: mediatek: Add configurable enable control to mtk_pll_data chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 09/22] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 10/22] clk: mediatek: Add MT8192 basic clocks support chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 11/22] clk: mediatek: Add MT8192 audio clock support chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 12/22] clk: mediatek: Add MT8192 camsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 13/22] clk: mediatek: Add MT8192 imgsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 14/22] clk: mediatek: Add MT8192 imp i2c wrapper " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 15/22] clk: mediatek: Add MT8192 ipesys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 16/22] clk: mediatek: Add MT8192 mdpsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 17/22] clk: mediatek: Add MT8192 mfgcfg " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 18/22] clk: mediatek: Add MT8192 mmsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 19/22] clk: mediatek: Add MT8192 msdc " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 20/22] clk: mediatek: Add MT8192 scp adsp " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 21/22] clk: mediatek: Add MT8192 vdecsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen 2021-05-05 10:07 ` [PATCH v8 22/22] clk: mediatek: Add MT8192 vencsys " chun-jie.chen 2021-05-05 10:07 ` chun-jie.chen
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