From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: matthew.brost@intel.com, tony.ye@intel.com, tvrtko.ursulin@intel.com, daniele.ceraolospurio@intel.com, carl.zhang@intel.com, jason.ekstrand@intel.com, jon.bloomfield@intel.com, daniel.vetter@intel.com, john.c.harrison@intel.com Subject: [RFC PATCH 5/5] drm/i915: Update execbuf IOCTL to accept N BBs Date: Thu, 6 May 2021 10:30:49 -0700 [thread overview] Message-ID: <20210506173049.72503-6-matthew.brost@intel.com> (raw) In-Reply-To: <20210506173049.72503-1-matthew.brost@intel.com> Add I915_EXEC_NUMBER_BB_* to drm_i915_gem_execbuffer2.flags which allows submitting N BBs per IOCTL. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Tony Ye <tony.ye@intel.com> CC: Carl Zhang <carl.zhang@intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- include/uapi/drm/i915_drm.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 0175b12b33b8..d3072cad4a7e 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1291,7 +1291,26 @@ struct drm_i915_gem_execbuffer2 { */ #define I915_EXEC_USE_EXTENSIONS (1 << 21) -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)) +/* + * Number of BB in execbuf2 IOCTL - 1, used to submit more than BB in a single + * execbuf2 IOCTL. + * + * Return -EINVAL if more than 1 BB (value 0) is specified if + * I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT hasn't been called on the gem + * context first. Also returns -EINVAL if gem context has been setup with + * I915_PARALLEL_NO_PREEMPT_MID_BATCH and the number BBs not equal to the total + * number hardware contexts in the gem context. + */ +#define I915_EXEC_NUMBER_BB_LSB (22) +#define I915_EXEC_NUMBER_BB_MASK (0x3f << I915_EXEC_NUMBER_BB_LSB) +#define I915_EXEC_NUMBER_BB_MSB (27) +#define i915_execbuffer2_set_number_bb(eb2, num_bb) \ + (eb2).flags = ((eb2).flags & ~I915_EXEC_NUMBER_BB_MASK) | \ + (((num_bb - 1) << I915_EXEC_NUMBER_BB_LSB) & I915_EXEC_NUMBER_BB_MASK) +#define i915_execbuffer2_get_number_bb(eb2) \ + ((((eb2).flags & I915_EXEC_NUMBER_BB_MASK) >> I915_EXEC_NUMBER_BB_LSB) + 1) + +#define __I915_EXEC_UNKNOWN_FLAGS (-(1 << (I915_EXEC_NUMBER_BB_MSB + 1))) #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) #define i915_execbuffer2_set_context_id(eb2, context) \ -- 2.28.0
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Brost <matthew.brost@intel.com> To: <intel-gfx@lists.freedesktop.org>, <dri-devel@lists.freedesktop.org> Cc: carl.zhang@intel.com, jason.ekstrand@intel.com, daniel.vetter@intel.com Subject: [Intel-gfx] [RFC PATCH 5/5] drm/i915: Update execbuf IOCTL to accept N BBs Date: Thu, 6 May 2021 10:30:49 -0700 [thread overview] Message-ID: <20210506173049.72503-6-matthew.brost@intel.com> (raw) In-Reply-To: <20210506173049.72503-1-matthew.brost@intel.com> Add I915_EXEC_NUMBER_BB_* to drm_i915_gem_execbuffer2.flags which allows submitting N BBs per IOCTL. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Tony Ye <tony.ye@intel.com> CC: Carl Zhang <carl.zhang@intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- include/uapi/drm/i915_drm.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 0175b12b33b8..d3072cad4a7e 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1291,7 +1291,26 @@ struct drm_i915_gem_execbuffer2 { */ #define I915_EXEC_USE_EXTENSIONS (1 << 21) -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1)) +/* + * Number of BB in execbuf2 IOCTL - 1, used to submit more than BB in a single + * execbuf2 IOCTL. + * + * Return -EINVAL if more than 1 BB (value 0) is specified if + * I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT hasn't been called on the gem + * context first. Also returns -EINVAL if gem context has been setup with + * I915_PARALLEL_NO_PREEMPT_MID_BATCH and the number BBs not equal to the total + * number hardware contexts in the gem context. + */ +#define I915_EXEC_NUMBER_BB_LSB (22) +#define I915_EXEC_NUMBER_BB_MASK (0x3f << I915_EXEC_NUMBER_BB_LSB) +#define I915_EXEC_NUMBER_BB_MSB (27) +#define i915_execbuffer2_set_number_bb(eb2, num_bb) \ + (eb2).flags = ((eb2).flags & ~I915_EXEC_NUMBER_BB_MASK) | \ + (((num_bb - 1) << I915_EXEC_NUMBER_BB_LSB) & I915_EXEC_NUMBER_BB_MASK) +#define i915_execbuffer2_get_number_bb(eb2) \ + ((((eb2).flags & I915_EXEC_NUMBER_BB_MASK) >> I915_EXEC_NUMBER_BB_LSB) + 1) + +#define __I915_EXEC_UNKNOWN_FLAGS (-(1 << (I915_EXEC_NUMBER_BB_MSB + 1))) #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) #define i915_execbuffer2_set_context_id(eb2, context) \ -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-05-06 17:13 UTC|newest] Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-06 17:30 [RFC PATCH 0/5] GuC submission / DRM scheduler integration plan + new uAPI Matthew Brost 2021-05-06 17:30 ` [Intel-gfx] " Matthew Brost 2021-05-06 17:27 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for " Patchwork 2021-05-06 17:30 ` [RFC PATCH 1/5] drm/doc/rfc: i915 GuC submission / DRM scheduler integration plan Matthew Brost 2021-05-06 17:30 ` [Intel-gfx] " Matthew Brost 2021-05-11 14:34 ` Daniel Vetter 2021-05-11 14:34 ` Daniel Vetter 2021-05-11 14:58 ` Daniel Stone 2021-05-11 14:58 ` Daniel Stone 2021-05-11 15:12 ` Daniel Vetter 2021-05-11 15:12 ` Daniel Vetter 2021-05-06 17:30 ` [RFC PATCH 2/5] drm/doc/rfc: i915 new parallel submission uAPI plan Matthew Brost 2021-05-06 17:30 ` [Intel-gfx] " Matthew Brost 2021-05-11 14:49 ` Daniel Vetter 2021-05-11 14:49 ` Daniel Vetter 2021-05-11 17:51 ` Matthew Brost 2021-05-11 17:51 ` Matthew Brost 2021-05-06 17:30 ` [RFC PATCH 3/5] drm/i915: Expose logical engine instance to user Matthew Brost 2021-05-06 17:30 ` [Intel-gfx] " Matthew Brost 2021-05-11 14:53 ` Daniel Vetter 2021-05-11 14:53 ` [Intel-gfx] " Daniel Vetter 2021-05-06 17:30 ` [RFC PATCH 4/5] drm/i915: Introduce 'set parallel submit' extension Matthew Brost 2021-05-06 17:30 ` [Intel-gfx] " Matthew Brost 2021-05-11 15:11 ` Daniel Vetter 2021-05-11 15:11 ` Daniel Vetter 2021-05-11 18:44 ` Matthew Brost 2021-05-11 18:44 ` Matthew Brost 2021-05-12 8:34 ` Daniel Vetter 2021-05-12 8:34 ` Daniel Vetter 2021-05-14 20:05 ` Matthew Brost 2021-05-14 20:05 ` Matthew Brost 2021-05-17 13:55 ` Daniel Vetter 2021-05-17 13:55 ` Daniel Vetter 2021-05-17 17:46 ` Matthew Brost 2021-05-17 17:46 ` Matthew Brost 2021-05-06 17:30 ` Matthew Brost [this message] 2021-05-06 17:30 ` [Intel-gfx] [RFC PATCH 5/5] drm/i915: Update execbuf IOCTL to accept N BBs Matthew Brost 2021-05-11 15:13 ` Daniel Vetter 2021-05-11 15:13 ` Daniel Vetter 2021-05-11 18:01 ` Matthew Brost 2021-05-11 18:01 ` Matthew Brost
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